Sheng Lin

CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

Kaiyuan Yang, Dai Li, Zhanghao Yu, 2021, IEEE Journal of Solid-State Circuits.

CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

Yong-Bin Kim, Fabrizio Lombardi, Sheng Lin, 2011, IEEE Transactions on Nanotechnology.

Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

Yong-Bin Kim, F. Lombardi, Sheng Lin, 2012, IEEE Transactions on Device and Materials Reliability.

Design of a Ternary Memory Cell Using CNTFETs

Yong-Bin Kim, F. Lombardi, Sheng Lin, 2012, IEEE Transactions on Nanotechnology.

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

Yong-Bin Kim, F. Lombardi, Sheng Lin, 2010, IEEE Transactions on Nanotechnology.

A novel CNTFET-based ternary logic gate design

F. Lombardi, Yong-bin Kim, Sheng-Jie Lin, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

A Highly-Stable Nanometer Memory for Low-Power Design

Yong-Bin Kim, F. Lombardi, Sheng Lin, 2008, 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems.

A 32nm SRAM design for low power and high stability

Yong-Bin Kim, F. Lombardi, Sheng Lin, 2008, 2008 51st Midwest Symposium on Circuits and Systems.

A low leakage 9t sram cell for ultra-low power operation

Yong-Bin Kim, Fabrizio Lombardi, Sheng Lin, 2008, GLSVLSI '08.

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

Yong-Bin Kim, Fabrizio Lombardi, Sheng Lin, 2010, Integr..

A new SRAM cell design using CNTFETs

Yong-Bin Kim, F. Lombardi, Sheng Lin, 2008, 2008 International SoC Design Conference.