Kensaku Matsunaga

On-chip detection methodology for break-even time of power gated function units

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Hiroshi Nakamura, Hideharu Amano, Hiroaki Kobayashi, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Design and evaluation of fine-grained power-gating for embedded microprocessors

Hiroshi Nakamura, Hideharu Amano, Hiroaki Kobayashi, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).