L. Hangbing

Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling

Steve S. Chung, Jing Li, Xiaoxin Xu, 2016, 2016 IEEE Symposium on VLSI Technology.

A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface

Kang Yi, Ren Qiwei, S. Hongbin, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Thermal effect on endurance performance of 3-dimensional RRAM crossbar array*

Ming Liu, Shibing Long, Qi Liu, 2016 .

CMOS Compatible Nonvolatile Memory Devices Based on SiO2/Cu/SiO2 Multilayer Films *

S. Long, Yingtao Li, H. Lv, 2011 .