D. Feltham

Physically realistic fault models for analog CMOS neural networks

Wojciech Maly, D.B.I. Feltham, Wojciech Maly, 1991 .

Full Hold-Scan Systems in Microprocessors: Cost/Benefit Analysis

Derek Feltham, Ravishankar Kuppuswamy, Rehan Sheikh, 2004 .

Current sensing for built-in testing of CMOS circuits

Wojciech Maly, P. J. Nigh, L. R. Carley, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

On New Test Points for Compact Cell-Aware Tests

Nilanjan Mukherjee, Friedrich Hapke, Janusz Rajski, 2016, IEEE Design & Test.

Embedded deterministic test points for compact cell-aware tests

Nilanjan Mukherjee, Friedrich Hapke, Janusz Rajski, 2015, 2015 IEEE International Test Conference (ITC).

STRaND-1: Use of a $500 Smartphone as the Central Avionics of a Nanosatellite

S. Kenyon, Christopher P. Bridges, J. Parsons, 2011 .

Design for testability view on placement and routing

Wojciech Maly, Derek Feltham, Jitendra Khare, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.