R. Katz

Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond

R. Katz, F. Khan, D. Moy, 2019, 2019 Symposium on VLSI Technology.

Face to Face Hybrid Wafer Bonding for Fine Pitch Applications

Daniel Smith, D. Fisher, J. Garant, 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

J. Woo, T. Kirihata, D. Moy, 2019, IEEE Electron Device Letters.

A high-density logic-on-logic 3DIC design using face-to-face hybrid wafer-bonding on 12nm FinFET process

B. Cline, J. Safran, D. Berger, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).