V. Maheshwari

Elmore's approximations based explicit delay and rise time model for distributed RLC on-chip VLSI global interconnect

R. Kar, D. Mandal, S. Agarwal, 2012, 2012 IEEE Symposium on Humanities, Science and Engineering Research.

4-π Crosstalk noise model for deep submicron VLSI global RC interconnects

R. Kar, D. Mandal, V. Maheshwari, 2012, 2012 IEEE Symposium on Humanities, Science and Engineering Research.

Delay and transient response modelling of on-chip RLCG interconnect using two-port network functions

R. Kar, D. Mandal, M. Datta, 2012, 2012 IEEE Symposium on Humanities, Science and Engineering Research.

2-π Crosstalk noise model for deep submicron VLSI global RC interconnects

R. Kar, D. Mandal, V. Maheshwari, 2012, 2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA).

Efficient coupled noise estimation for RLC on-chip interconnect

S. Gupta, R. Kar, D. Mandal, 2012, 2012 IEEE Symposium on Humanities, Science and Engineering Research.

Moment based delay modelling for on-chip RC global VLSI interconnect for unit ramp input

R. Kar, D. Mandal, V. Maheshwari, 2012, 2012 Ninth International Conference on Computer Science and Software Engineering (JCSSE).