Staf Verhaegen

发表

Feasibility of printing 0.1-μm technology with optical lithography

Kurt G. Ronse, Winfried Kaiser, Mireille Maenhoudt, 1999, Advanced Lithography.

Double patterning design split implementation and validation for the 32nm node

Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, 2007, SPIE Advanced Lithography.

OPC aware mask and wafer metrology

Vincent Wiaux, Kurt G. Ronse, Vicky Philipsen, 2002, European Mask and Lithography Conference.

Challenge for sub-100-nm DRAM gate printing using ArF lithography with combination of moderate OAI and attPSM

Geert Vandenberghe, Kurt G. Ronse, Staf Verhaegen, 2002, SPIE Photomask Technology.

Interactions of double patterning technology with wafer processing, OPC and design flows

Vincent Wiaux, Staf Verhaegen, Kevin Lucas, 2008, SPIE Advanced Lithography.

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

Vincent Wiaux, Staf Verhaegen, Kevin Lucas, 2009 .

Reticle quality needs for advanced 193-nm lithography

Vincent Wiaux, Geert Vandenberghe, Kurt G. Ronse, 2001, Photomask Japan.

Analysis of the impact of reticle CD variations on the available process windows for a 100 nm CMOS process

Geert Vandenberghe, Kurt G. Ronse, Staf Verhaegen, 2002, Photomask Technology.

Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning

Vincent Wiaux, Staf Verhaegen, Nadia Vandenbroeck, 2010, Advanced Lithography.

Litho variations and their impact on the electrical yield of a 32nm node 6TSRAM cell design for manufacturability through design-proces integration II

Geert Vandenberghe, Wim Dehaene, Staf Verhaegen, 2008 .

Split and design guidelines for double patterning

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2008, SPIE Advanced Lithography.

Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell

Geert Vandenberghe, Wim Dehaene, Staf Verhaegen, 2008, SPIE Advanced Lithography.

Litho enhancements for 45nm-node MuGFETs

Geert Vandenberghe, Staf Verhaegen, Monique Ercken, 2005 .

A methodology for double patterning compliant split and design

Vincent Wiaux, Geert Vandenberghe, Mireille Maenhoudt, 2008, Lithography Asia.

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Geert Vandenberghe, Staf Verhaegen, Mircea Dusa, 2007, SPIE Advanced Lithography.

Printability verification for double-patterning technology

Vincent Wiaux, Mireille Maenhoudt, Staf Verhaegen, 2008, Photomask Technology.

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

Vincent Wiaux, Rita Rooyackers, Staf Verhaegen, 2004 .

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Vincent Wiaux, Mireille Maenhoudt, Staf Verhaegen, 2008, SPIE Advanced Lithography.

Experimental verification of source-mask optimization and freeform illumination for 22-nm node static random access memory cells

Geert Vandenberghe, Jens Timo Neumann, Mircea Dusa, 2011 .

Immersion lithography and double patterning in advanced microelectronics

Vincent Wiaux, Geert Vandenberghe, Mireille Maenhoudt, 2010, International Conference on Micro- and Nano-Electronics.

Optical extensions integration for a 0.314-μm2 45-nm node 6-transistor SRAM cell

Vincent Wiaux, Geert Vandenberghe, Eric Hendrickx, 2005, SPIE Advanced Lithography.

Double pattern EDA solutions for 32nm HP and beyond

Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, 2007, SPIE Advanced Lithography.

Model-based OPC for first-generation 193-nm lithography

Geert Vandenberghe, Kevin D. Lucas, Staf Verhaegen, 2001, SPIE Advanced Lithography.

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Staf Verhaegen, Monique Ercken, Mircea Dusa, 2011, Advanced Lithography.

Limits of optical lithography

Kurt G. Ronse, Mireille Maenhoudt, Staf Verhaegen, 2000, Advanced Lithography.

CD control for two-dimensional features in future technology nodes

Martin McCallum, Staf Verhaegen, Kurt G. Ronse, 2001, SPIE Advanced Lithography.

Assessment of OPC effectiveness using two-dimensional metrics

Vincent Wiaux, Geert Vandenberghe, Kurt G. Ronse, 2002, SPIE Advanced Lithography.

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

Geert Vandenberghe, Jo Finders, Staf Verhaegen, 2006, SPIE Advanced Lithography.

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Joint-optimization for SRAM and logic for 28nm node and below

Michael C. Smayling, Peter De Bisschop, Staf Verhaegen, 2010, Advanced Lithography.

Exploration of etch step interactions in the dual patterning process for process modeling

Vincent Wiaux, Lawrence S. Melvin, Mireille Maenhoudt, 2008 .