Riichiro Takemura

发表

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays

Kiyoo Itoh, Satoru Akiyama, Tomonori Sekiguchi, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

Kiyoo Itoh, Tomonori Sekiguchi, Yoshimitsu Yanagawa, 2012, IEICE Trans. Electron..

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing

Kiyoo Itoh, Satoru Akiyama, Tomonori Sekiguchi, 2012, IEICE Trans. Electron..

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

Shoji Ikeda, Takayuki Kawahara, Hiroyuki Yamamoto, 2010, IEEE Journal of Solid-State Circuits.

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems

Takayuki Kawahara, Hideo Ohno, Riichiro Takemura, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs

Masashi Horiguchi, Kiyoo Itoh, Ryuta Tsuchiya, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device

Takayuki Kawahara, Tatsuo Nakagawa, Yoshimitsu Yanagawa, 2012, IEICE Trans. Electron..

0.5-V high-speed circuit designs for nanoscale SoCs — Challenges and solutions

Kiyoo Itoh, Ryuta Tsuchiya, Akira Kotabe, 2011, 2011 International Symposium on Integrated Circuits.

Resistive-switching Solid-state Brain-neocortex-like Device for Advanced Non-volatile Logic Applications

Yoshihisa Fujisaki, Motoyasu Terao, Masaharu Kinoshita, 2009 .

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation

Kiyoo Itoh, Satoru Akiyama, Takayuki Kawahara, 2007, IEICE Trans. Electron..

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read

Shoji Ikeda, Takayuki Kawahara, Hideo Ohno, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Spin-transfer torque RAM technology: Review and prospect

Takayuki Kawahara, Hideo Ohno, Riichiro Takemura, 2012, Microelectron. Reliab..

Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device

Takayuki Kawahara, Tatsuo Nakagawa, Yoshimitsu Yanagawa, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond

Takayuki Kawahara, Hideo Ohno, Riichiro Takemura, 2011 .

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup

Takeshi Sakata, Takayuki Kawahara, Kazuhiko Kajigaya, 2005, IEEE International Conference on Communications, 2005. ICC 2005. 2005.

Low-Power NV-RAM

Riichiro Takemura, 2013 .

Low-voltage limitations and challenges of memory-rich nano-scale CMOS LSIs

Kiyoo Itoh, Riichiro Takemura, 2007, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs

Kiyoo Itoh, Akira Kotabe, Riichiro Takemura, 2012, IEICE Trans. Electron..

Characterization of GaInAs/InP Triple-Barrier Resonant Tunneling Diodes Grown by Organo-Metallic Vapor Phase Epitaxy for High-Temperature Estimation of Phase Coherent Length of Electrons

Michihiko Suhara, Yasuyuki Miyamoto, Riichiro Takemura, 1997 .

High peak-to-valley current ratio GaInAs/GaInP resonant tunneling diodes

Michihiko Suhara, Yasuyuki Miyamoto, Riichiro Takemura, 1997 .

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory

Naoki Kitai, Kenichi Osada, Takayuki Kawahara, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers

Kiyoo Itoh, Tomonori Sekiguchi, Riichiro Takemura, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond

Yoshihisa Fujisaki, Motoyasu Terao, Kenzo Kurotsuchi, 2009 .