Takayasu Sakurai

发表

Design Method of Class-F Power Amplifier With Output Power of $-$ 20 dBm and Efficient Dual Supply Voltage Transmitter

Akira Saito, Shunta Iguchi, Kazunori Watanabe, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

EP2: The semiconductor industry in 2025

Shekhar Y. Borkar, Takayasu Sakurai, Siva G. Narendra, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications

Takayasu Sakurai, Koichi Nose, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Hot-carrier generation in submicrometer VLSI environment

Tetsuya Iizuka, Takayasu Sakurai, Kazutaka Nogami, 1986 .

Integrated Circuits: 50 Years of Their Evolution and Future Prospects ―Towards Higher-Density Memories and Ultra-Low Power LSIs―

Kenji Taniguchi, Takayasu Sakurai, Toshiro Hiramoto, 2013 .

CR Isolated Cell for Soft Error Prevention -Static RAM Application

Tetsuya Iizuka, Takayasu Sakurai, 1983, 1983 Symposium on VLSI Technology. Digest of Technical Papers.

Perspectives of Low-Power VLSI's

Takayasu Sakurai, T. Sakurai, 2004 .

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode

Tetsuya Iizuka, Takayasu Sakurai, M. Isobe, 1988 .

A 72 K CMOS channellers gate array with embedded 1 Mbit dynamic RAM

Tetsuya Iizuka, Takayasu Sakurai, Y. Tanaka, 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Tadahiro Kuroda, Takayasu Sakurai, Noriyuki Miura, 2009, IEEE J. Solid State Circuits.

LSI design toward 2010 and low-power technology

Takayasu Sakurai, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

Variable supply-voltage scheme for low-power high-speed CMOS digital design

Tadahiro Kuroda, T. Maeda, Takayasu Sakurai, 1998, IEEE J. Solid State Circuits.

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and ${\rm V}_{\rm TH}$-Tuned Oscillator With Fixed Charge Programming

Koichi Ishida, Takayasu Sakurai, Po-Hung Chen, 2012, IEEE Journal of Solid-State Circuits.

Power Device Degradation Estimation by Machine Learning of Gate Waveforms

Katsuhiro Hata, Takayasu Sakurai, Makoto Takamiya, 2020, 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization

Takayasu Sakurai, T. Sakurai, 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems

Takayasu Sakurai, Makoto Takamiya, Gil-Su Kim, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Tadahiro Kuroda, Takayasu Sakurai, 1996, J. VLSI Signal Process..

A 36ns 1Mbit Pseudo SRAM with VSRAM mode

Tetsuya Iizuka, Katsuhiko Sato, Takayasu Sakurai, 1987, 1987 Symposium on VLSI Circuits.

VLSI circuit reliability under AC hot-carrier stress

Takayasu Sakurai, Kazutaka Nogami, Kazuhiro Sawada, 1987, 1987 Symposium on VLSI Circuits.

Automatic Search Method of Robust Gate Driving Vectors for Digital Gate Drivers Against Variations in Operating Conditions of IGBT’s

Katsuhiro Hata, Takayasu Sakurai, Makoto Takamiya, 2020, 2020 IEEE Energy Conversion Congress and Exposition (ECCE).

VLSI-Oriented Voltage Down Converter with Sub-Main Configuration

Tetsuya Iizuka, Takayasu Sakurai, Kazuhiro Sawada, 1984 .

A SIMPLE MOSFET MODEL FOR CIRCUIT ANALYSIS AND ITS APPLICATION TO CMOS GATE DELAY ANALYSIS AND SERIES-CONNECTED MOSFET STRUCTURE

A. Richard Newton, Takayasu Sakurai, 1990 .

Examinations of the Relative Alignment of the Instruments on SOT

Yukio Katsukawa, Toshifumi Shimizu, Takayasu Sakurai, 2007 .

Transparent-refresh DRAM (TReD) using dual-port DRAM cell

Tetsuya Iizuka, Takayasu Sakurai, Kazutaka Nogami, 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

200 MHz video compression macrocells using low-swing differential logic

Lee-Sup Kim, Takayasu Sakurai, Y. Uetani, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

On-Chip Battery Back-Up Circuit for VLSI Static RAM's

Tetsuya Iizuka, Takayasu Sakurai, Kazuhiro Sawada, 1985 .

A 1Mb virtually SRAM

Tetsuya Iizuka, Takayasu Sakurai, M. Isobe, 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Architecture and Design Methodology of 32KByte Integrated Cache Memory

Tetsuya Iizuka, Kenji Maeguchi, Takayasu Sakurai, 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.

Self-Aligned Refresh Scheme for VLSI Intelligent Dynamic RAMs

Tetsuya Iizuka, Takayasu Sakurai, Mitsuo Isobe, 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers.

INVITED PAPER Special Section on Low-Power System LSI, IP and Related Technologies Perspectives of Low-Power VLSI's

Takayasu Sakurai, 2004 .

Digital Transmitter Coil for Wireless Power Transfer Robust Against Variation of Distance and Lateral Misalignment

Takayasu Sakurai, Makoto Takamiya, Hao Qiu, 2020, IEEE Transactions on Microwave Theory and Techniques.

Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

Akira Matsuzawa, Takayasu Sakurai, Takakuni Douseki, 2006 .