R. Farjad-Rad

0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization

R. Senthinathan, W.J. Dally, R. Farjad-Rad, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

R. Senthinathan, W.J. Dally, R. Farjad-Rad, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips

R. Farjad-Rad, R. Rathi, J. Poulton, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

R. Senthinathan, J.M. Tran, W.J. Dally, 2004, IEEE Journal of Solid-State Circuits.

A second-order semi-digital clock recovery circuit based on injection locking

R. Senthinathan, Hiok-Tiaq Ng, R. Farjad-Rad, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..