S. Orain

A multi scale finite element methodology to evaluate wire bond pad architectures

V. Fiori, S. Orain, V. Fiori, 2005, EuroSimE 2005. Proceedings of the 6th International Conference on Thermal, Mechanial and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005..

Virtual Prototyping based Design Optimization of the Substrate, Leadframe, and Flip Chip Package Families with Low-k Technology

S. Orain, W.D. van Driel, T. Hauck, 2006, EuroSime 2006 - 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems.

FEM-based method to determine mechanical stress evolution during process flow in microelectronics. Application to stress-voiding

S. Orain, X. Federspiel, J.-C. Barbé, 2004, 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the.

A constitutive single crystal model for the silicon mechanical behavior: applications to the stress induced by silicided lines and STI in MOS technologies

S. Orain, Florian Cacho, G. Cailletaud, 2005, EuroSimE 2005. Proceedings of the 6th International Conference on Thermal, Mechanial and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005..

Use of genetic algorithms for the simultaneous estimation of thin films thermal conductivity and contact resistances

S. Orain, Y. Scudeller, Thierry Brousse, 2001 .

Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features

Pierre Morin, S. Orain, C. Ortolland, 2006 .

Integration of a mechanically reliable 65-nm node technology for low-k and ULK interconnects with various substrate and package types

V. Fiori, S. Orain, C. Goldberg, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

S. Orain, C. Ortolland, P. Stolk, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments

V. Fiori, S. Orain, S. Gallois-Garreignot, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS

V. Fiori, S. Orain, D. Delille, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Gold Wire Bonding Induced Peeling in Cu/Low-k Interconnects: 3D Simulation and Correlations

V. Fiori, S. Orain, S. Gallois-Garreignot, 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress

G. Reimbold, G. Ghibaudo, S. Orain, 2004, IEEE Transactions on Electron Devices.

Reliability issues in Cu/low-k structures regarding the initiation of stress-voiding or crack failure

V. Fiori, S. Orain, X. Federspiel, 2006 .

Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors

V. Fiori, S. Orain, C. Ortolland, 2007, IEEE Transactions on Electron Devices.