Giacinto Paolo Saggese

发表

FPGA-based implementation of a serial RSA processor

Antonino Mazzeo, Nicola Mazzocca, Luigi Romano, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Hardware support for high performance, intrusion- and fault-tolerant systems

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Luigi Romano, 2004, Proceedings of the 23rd IEEE International Symposium on Reliable Distributed Systems, 2004..

Shuffled serial adder: an area-latency effective serial adder

Nicola Mazzocca, Davide De Caro, Antonio G. M. Strollo, 2002, 9th International Conference on Electronics, Circuits and Systems.

Automated Derivation of Application-Specific Error Detectors Using Dynamic Analysis

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Karthik Pattabiraman, 2011, IEEE Transactions on Dependable and Secure Computing.

A tamper resistant hardware accelerator for RSA cryptographic applications

Antonino Mazzeo, Nicola Mazzocca, Luigi Romano, 2004, J. Syst. Archit..

An Architectural Framework for Detecting Process Hangs/Crashes

Ravishankar K. Iyer, Nithin Nakka, Zbigniew T. Kalbarczyk, 2005, EDCC.

Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Karthik Pattabiraman, 2006, 2006 Sixth European Dependable Computing Conference.

An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm

Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo, 2003, FPL.

A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations

Beniamino Di Martino, Nicola Mazzocca, Antonio G. M. Strollo, 2002, FPL.

Exploring the design-space for FPGA-based implementation of RSA

Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, 2004, Microprocess. Microsystems.

Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Giacinto Paolo Saggese, 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

Carry-save Montgomery modular exponentiation on reconfigurable hardware

Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A Web Services Based Architecture for Digital Time Stamping

Alessandro Cilardo, Giuseppe Cattaneo, Antonino Mazzeo, 2004, J. Web Eng..

A reconfigurable 2D convolver for real-time SAR imaging

Davide De Caro, Antonio G. M. Strollo, Giacinto Paolo Saggese, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

An experimental study of soft errors in microprocessors

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Sanjay J. Patel, 2005, IEEE Micro.

Using Web Services Technology for Inter-enterprise Integration of Digital Time Stamping

Alessandro Cilardo, Giuseppe Cattaneo, Antonino Mazzeo, 2003, OTM Workshops.