R. Nandwana

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

High-Performance CMOS TIA for Data Center Optical Interconnects

P. Hanumolu, V. Boccuzzi, K. Lakshmikumar, 2022, 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS).

A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling

Ahmed Elkholy, Pavan Kumar Hanumolu, Romesh Kumar Nandwana, 2021, IEEE Journal of Solid-State Circuits.

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS

Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski, Qadeer Ahmad Khan, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2019, IEEE Journal of Solid-State Circuits.

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2016, IEEE Journal of Solid-State Circuits.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2015, IEEE Journal of Solid-State Circuits.

A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with −14dBm Optical Sensitivity in 16nm CMOS

P. Hanumolu, K. Lakshmikumar, R. Nandwana, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Amr Elshazly, Pavan Kumar Hanumolu, Kartikeya Mayaram, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.