Huan-Shun Huang

Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic

Chung-Yu Wu, Huan-Shun Huang, Chung-Yu Wu, 1993 .

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Chien-Yu Lu, Ming-Chien Tsai, Ming-Hsien Tu, 2012, IEEE Journal of Solid-State Circuits.