Yu-Shen Yang

发表

Automated data analysis techniques for a modern silicon debug environment

Masahiro Fujita, Andreas G. Veneris, Yu-Shen Yang, 2012, 17th Asia and South Pacific Design Automation Conference.

A failure triage engine based on error trace signature extraction

Andreas G. Veneris, Zissis Poulos, Yu-Shen Yang, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Automated Logic Restructuring with aSPFDs

Robert K. Brayton, Andreas Veneris, Yu-Shen Yang, 2011 .

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

Andreas G. Veneris, Yu-Shen Yang, Nicola Nicolici, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Automated data analysis solutions to silicon debug

Andreas G. Veneris, Yu-Shen Yang, Nicola Nicolici, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Seamless Integration ofSERinRewiring-Based Design SpaceExploration

Yiorgos Makris, Andreas Veneris, Yu-Shen Yang, 2006 .

Automated software solutions to logic restructuring and silicon debug

Yu-Shen Yang, 2010 .

Simulation and satisfiability guided counter-example triage for RTL design debugging

Andreas G. Veneris, Zissis Poulos, Yu-Shen Yang, 2014, Fifteenth International Symposium on Quality Electronic Design.

Automating Logic Transformations With Approximate SPFDs

Robert K. Brayton, Andreas G. Veneris, Yu-Shen Yang, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Extraction error modeling and automated model debugging in high-performance custom designs

Andreas G. Veneris, Paul J. Thadikaran, Yu-Shen Yang, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Extraction error diagnosis and correction in high-performance designs

Andreas G. Veneris, Paul J. Thadikaran, Jiang Brandon Liu, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD

Andreas G. Veneris, Yiorgos Makris, Yu-Shen Yang, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Extraction error analysis, diagnosis and correction in custom-made high-performance designs

Andreas G. Veneris, Paul J. Thadikaran, Jiang Brandon Liu, 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.

Automating Logic Rectification by Approximate SPFDs

Robert K. Brayton, Andreas G. Veneris, Yu-Shen Yang, 2007, 2007 Asia and South Pacific Design Automation Conference.

Extraction error modeling and automated model debugging in high-performance low power custom designs

Andreas G. Veneris, Paul J. Thadikaran, Yu-Shen Yang, 2005, Design, Automation and Test in Europe.

Leveraging reconfigurability to raise productivity in FPGA functional debug

Andreas G. Veneris, Zissis Poulos, Jason Helge Anderson, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Automated silicon debug data analysis techniques for a hardware data acquisition environment

Sean Safarpour, Andreas G. Veneris, Yu-Shen Yang, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Seamless Integration of SER in Rewiring-Based Design Space Exploration

Andreas G. Veneris, Yiorgos Makris, Yu-Shen Yang, 2006, 2006 IEEE International Test Conference.

Sequential logic rectifications with approximate SPFDs

Robert K. Brayton, Andreas G. Veneris, Yu-Shen Yang, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.