Nicola Nicolici

发表

Automated data analysis techniques for a modern silicon debug environment

Masahiro Fujita, Andreas G. Veneris, Yu-Shen Yang, 2012, 17th Asia and South Pacific Design Automation Conference.

A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test

Nicola Nicolici, Ho Fai Ko, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug

Nicola Nicolici, Amin Vali, 2015, 2015 IEEE 24th North Atlantic Test Workshop.

Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

Nicola Nicolici, Adam B. Kinsman, N. Nicolici, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

Andreas G. Veneris, Yu-Shen Yang, Nicola Nicolici, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Power constrained test scheduling using power profile manipulation

Bashir M. Al-Hashimi, Nicola Nicolici, P. Rosinger, 2001 .

Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing"

Bashir M. Al-Hashimi, Nicola Nicolici, 1998, IEEE Trans. Computers.

Power-constrained testing of VLSI circuits

Bashir M. Al-Hashimi, Nicola Nicolici, 2003 .

Power constrained test scheduling using power profile manipulation

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Guest Editors' Introduction: Silicon Debug and Diagnosis

Nicola Nicolici, Brady Benware, 2013 .

Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging

Nicola Nicolici, Ho Fai Ko, 2010, 2010 15th IEEE European Test Symposium.

Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test

Nicola Nicolici, Ho Fai Ko, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testability trade-offs for BIST RTL data paths: the case for three dimensional design space

Bashir M. Al-Hashimi, Nicola Nicolici, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Guest Editorial

Patrick Girard, Nicola Nicolici, 2008, J. Electron. Test..

Low Power Testing of Digital ICs: Overview

Bashir M. Al-Hashimi, Nicola Nicolici, 2000 .

Automated data analysis solutions to silicon debug

Andreas G. Veneris, Yu-Shen Yang, Nicola Nicolici, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Computational bit-width allocation for operations in vector calculus

Nicola Nicolici, Adam B. Kinsman, 2009, 2009 IEEE International Conference on Computer Design.

Bit-Flip Detection-Driven Selection of Trace Signals

Nicola Nicolici, Amin Vali, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-frequency test access mechanism design for modular SOC testing

Qiang Xu, Nicola Nicolici, N. Nicolici, 2004, 13th Asian Test Symposium.

Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy

Nicola Nicolici, Ho Fai Ko, N. Nicolici, 2008, J. Electron. Test..

Emulation-based selection and assessment of assertion checkers for post-silicon validation

Nicola Nicolici, Pouya Taatizadeh, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Wrapper design for multifrequency IP cores

Qiang Xu, Nicola Nicolici, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dual multiple-polynomial LFSR for low-power mixed-mode BIST

Bashir M. Al-Hashimi, Nicola Nicolici, P. Rosinger, 2003 .

On improving real-time observability for in-system post-silicon debug

Nicola Nicolici, 2010, 2010 11th Latin American Test Workshop.

Post-silicon validation opportunities, challenges and recent advances

Sanjit A. Seshia, Nicola Nicolici, Subhasish Mitra, 2010, Design Automation Conference.

Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation

Nicola Nicolici, Pouya Taatizadeh, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation

Nicola Nicolici, Zahra Lak, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

Automated Range and Precision Bit-Width Allocation for Iterative Computations

Nicola Nicolici, Adam B. Kinsman, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multifrequency TAM design for hierarchical SOCs

Qiang Xu, Nicola Nicolici, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Embedded memory binding in FPGAs

Nicola Nicolici, Kaveh Elizeh, 2010, Design Automation Conference.

Qiang Xu, Nicola Nicolici, Ho Fai Ko, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Resource-Efficient Programmable Trigger Units for Post-Silicon Validation

Nicola Nicolici, Ho Fai Ko, 2009, 2009 14th IEEE European Test Symposium.

NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging

Nicola Nicolici, Phillip Kinsman, 2013, IEEE Transactions on Computers.

Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits

Bashir M. Al-Hashimi, Nicola Nicolici, B. Al-Hashimi, 2002, IEEE Trans. Computers.

DATE 07 workshop on diagnostic services in NoCs

Axel Jantsch, Erik Jan Marinissen, Nicola Nicolici, 2007, IEEE Des. Test Comput..

A novel optimal single constant multiplication algorithm

Nicola Nicolici, Jason Thong, 2010, Design Automation Conference.

On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging

Nicola Nicolici, Zahra Lak, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A methodology for automated design of embedded bit-flips detectors in post-silicon validation

Nicola Nicolici, Pouya Taatizadeh, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture

Shahin Sirouspour, Nicola Nicolici, Behzad Mahdavikhah, 2010, FPGA '10.

DFT infrastructure for broadside two-pattern test of core-based SOCs

Qiang Xu, Nicola Nicolici, 2006, IEEE Transactions on Computers.

Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing

Nicola Nicolici, A. B. Kinsman, 2008, ISQED 2008.

Scan architecture for shift and capture cycle power reduction

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses

Nicola Nicolici, Adam B. Kinsman, 2011, IEEE Transactions on Computers.

Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels

Nicola Nicolici, Adam B. Kinsman, 2005, European Test Symposium (ETS'05).

Synchronization overhead in SOC compressed test

Bashir M. Al-Hashimi, Nicola Nicolici, Paul Theo Gonciari, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Finite Precision bit-width allocation using SAT-Modulo Theory

Nicola Nicolici, Adam B. Kinsman, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Diagnostic Services in Network Diagnostic Services in Network - - on on - - Chips Chips ⎯ ⎯ Test, Debug, and On Test, Debug, and On - Line Monitoring Line Monitoring ⎯

Axel Jantsch, Nicola Nicolici, 2008 .

Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores

Qiang Xu, Nicola Nicolici, 2004, 2004 International Conferce on Test.

A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation

Shahin Sirouspour, Nicola Nicolici, Behzad Mahdavikhah, 2014, ACM Trans. Embed. Comput. Syst..

Efficient BIST hardware insertion with low test application time for synthesized data paths

Nicola Nicolici, Bashir M. Al-Hashimi, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits

Bashir M. Al-Hashimi, Nicola Nicolici, 2000, DATE '00.

Useless Memory Allocation: Problems and Solutions

Nicola Nicolici, Bashir M. Al-Hashimi, P. T. Gonciari, 2002 .

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation

Nicola Nicolici, Ho Fai Ko, Adam B. Kinsman, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Design-for-debug for post-silicon validation: Can high-level descriptions help?

Nicola Nicolici, Ho Fai Ko, 2009, 2009 IEEE International High Level Design Validation and Test Workshop.

Bit-flip detection-driven selection of trace signals

Nicola Nicolici, Amin Vali, 2016, 2016 21th IEEE European Test Symposium (ETS).

Hardware-based parallel computing for real-time haptic rendering of deformable objects

Shahin Sirouspour, Nicola Nicolici, Mahyar Fotoohi, 2008, 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems.

An automated SAT-based method for the design of on-chip bit-flip detectors

Nicola Nicolici, Pouya Taatizadeh, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

On-Chip Constrained-Random Stimuli Generation

Nicola Nicolici, Xiaobing Shi, 2019 .

On-chip stimuli generation for post-silicon validation

Nicola Nicolici, 2012, 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT).

Power profile manipulation: a new approach for reducing test application time under power constraints

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

SAT solving using FPGA-based heterogeneous computing

Nicola Nicolici, Jason Thong, N. Nicolici, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

Bashir M. Al-Hashimi, Nicola Nicolici, P. Rosinger, 2001 .

On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli

Nicola Nicolici, Xiaobing Shi, 2014, 2014 IEEE 23rd Asian Test Symposium.

Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs

Nicola Nicolici, Ho Fai Ko, Adam B. Kinsman, 2008, 2008 IEEE International Test Conference.

Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation

Nicola Nicolici, Xiaobing Shi, N. Nicolici, 2016, IEEE Transactions on Computers.

Embedded Tutorial on Low Power Test

Xiaoqing Wen, Nicola Nicolici, 2007, 12th IEEE European Test Symposium (ETS'07).

Compressed embedded diagnosis of logic cores

Nicola Nicolici, Adam B. Kinsman, Scott Ollivierre, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Dynamic binary translation to a reconfigurable target for on-the-fly acceleration

Nicola Nicolici, Phillip Kinsman, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Variable-length input Huffman coding for system-on-a-chip test

Bashir M. Al-Hashimi, Nicola Nicolici, Paul Theo Gonciari, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test cost reduction through compression

Nicola Nicolici, P. T. Gonciari, Bashi Al-Hashimi, 2003 .

RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints

Nicola Nicolici, Ho Fai Ko, 2006, 2006 International Conference on Computer Design.

A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications

Dan Werthimer, Henry Chen, Borivoje Nikolic, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Hardware/software co-testing of embedded memories in complex SOCs

Qiang Xu, Nicola Nicolici, Bai Hong Fang, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

On concurrent test of wrapped cores and unwrapped logic blocks in SOCs

Qiang Xu, Nicola Nicolici, 2005, IEEE International Conference on Test, 2005..

On using lossless compression of debug data in embedded logic analysis

Nicola Nicolici, Ehab Anis Daoud, N. Nicolici, 2007, 2007 IEEE International Test Conference.

A generic embedded sequence generator for constrained-random validation with weighted distributions

Nicola Nicolici, Xiaobing Shi, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Modular and rapid testing of SOCs with unwrapped logic blocks

Qiang Xu, Nicola Nicolici, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Minimising power dissipation in partial scan sequential circuits

Bashir M. Al-Hashimi, Nicola Nicolici, 2001 .

Power-Aware Testing and Test Strategies for Low Power Devices

Kaushik Roy, Xiaoqing Wen, Patrick Girard, 2008, 2008 Design, Automation and Test in Europe.

Power-conscious test synthesis and scheduling

Bashir M. Al-Hashimi, Nicola Nicolici, 2003, IEEE Design & Test of Computers.

Power Profile Manipulation

Bashir M. Al-Hashimi, Nicola Nicolici, P. Rosinger, 2004 .

Robust design methods for hardware accelerators for iterative algorithms in scientific computing

Nicola Nicolici, Adam B. Kinsman, 2010, Design Automation Conference.

Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug

Nicola Nicolici, Ho Fai Ko, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Time-Multiplexed Compressed Test of SOC Designs

Nicola Nicolici, Adam B. Kinsman, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Useless memory allocation in system-on-a-chip test: problems and solutions

Bashir M. Al-Hashimi, Nicola Nicolici, Paul Theo Gonciari, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Low Cost Debug Architecture using Lossy Compression for Silicon Debug

Nicola Nicolici, Ehab Anis Daoud, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

Nicola Nicolici, Jason Thong, N. Nicolici, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

On Using Lossy Compression for Repeatable Experiments during Silicon Debug

Nicola Nicolici, Ehab Anis Daoud, 2011, IEEE Transactions on Computers.

A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies

Shahin Sirouspour, Nicola Nicolici, Adam B. Kinsman, 2010, IEEE Transactions on Haptics.

Addressing useless test data in core-based system-on-a-chip test

Bashir M. Al-Hashimi, Nicola Nicolici, Paul Theo Gonciari, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing

Bashir M. Al-Hashimi, Nicola Nicolici, Paul Theo Gonciari, 2002, Proceedings. International Test Conference.

Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation

Nicola Nicolici, Ehab Anis Daoud, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation

Nicola Nicolici, Xiaobing Shi, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Functional Illinois scan design at RTL

Nicola Nicolici, Ho Fai Ko, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research

George A. Constantinides, Nicola Nicolici, 2011, IEEE Des. Test Comput..

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Combined optimal and heuristic approaches for multiple constant multiplication

Nicola Nicolici, Jason Thong, 2010, 2010 IEEE International Conference on Computer Design.

Modular SOC testing with reduced wrapper count

Qiang Xu, Nicola Nicolici, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-frequency wrapper design and optimization for embedded cores under average power constraints

Qiang Xu, Krishnendu Chakrabarty, Nicola Nicolici, 2005, Proceedings. 42nd Design Automation Conference, 2005..

A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test

Nicola Nicolici, Ho Fai Ko, 2008, ISQED 2008.

Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns

Nicola Nicolici, Jason Thong, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation

Nicola Nicolici, Ho Fai Ko, 2008, 2008 Design, Automation and Test in Europe.

BIST hardware synthesis for RTL data paths based on testcompatibility classes

Bashir M. Al-Hashimi, Nicola Nicolici, Andrew D. Brown, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Editorial Silicon Debug and Diagnosis

Erik Jan Marinissen, Nicola Nicolici, 2007, IET Comput. Digit. Tech..

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression

Bashir M. Al-Hashimi, Nicola Nicolici, Paul Theo Gonciari, 2002, DATE.

Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing

Nicola Nicolici, Adam B. Kinsman, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Functional scan chain design at RTL for skewed-load delay fault testing

Nicola Nicolici, Ho Fai Ko, N. Nicolici, 2004, 13th Asian Test Symposium.

Test data compression: the system integrator's perspective

Bashir M. Al-Hashimi, Nicola Nicolici, Paul Theo Gonciari, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Qiang Xu, Krishnendu Chakrabarty, Nicola Nicolici, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Nicola Nicolici, Ho Fai Ko, Adam B. Kinsman, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A New Algorithm for Post-Silicon Clock Measurement and Tuning

Nicola Nicolici, Zahra Lak, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

Power conscious test synthesis and scheduling for BIST RTL data paths

Bashir M. Al-Hashimi, Nicola Nicolici, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

On Automated Trigger Event Generation in Post-Silicon Validation

Nicola Nicolici, Ho Fai Ko, 2008, 2008 Design, Automation and Test in Europe.

Guest Editors' Introduction: Top Papers from the 2015 International Test Conference

Haralampos-G. D. Stratigopoulos, Nicola Nicolici, 2016, IEEE Des. Test.

Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation

Nicola Nicolici, Pouya Taatizadeh, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Delay fault testing of core-based systems-on-a-chip

Qiang Xu, Nicola Nicolici, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison

Nicola Nicolici, Adam B. Kinsman, Scott Ollivierre, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Automated silicon debug data analysis techniques for a hardware data acquisition environment

Sean Safarpour, Andreas G. Veneris, Yu-Shen Yang, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

On-chip generation of uniformly distributed constrained-random stimuli for post-silicon validation

Nicola Nicolici, Xiaobing Shi, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Numerical Data Representations for FPGA-Based Scientific Computing

George A. Constantinides, Nicola Nicolici, Adam B. Kinsman, 2011, IEEE Design & Test of Computers.

Power-constrained embedded memory BIST architecture

Nicola Nicolici, Bai Hong Fang, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Session details: Testing for process- and timing-related faults

Kazumi Hatayama, Nicola Nicolici, Gordon Roberts, 2005, DAC '05.

An Optimal and Practical Approach to Single Constant Multiplication

Nicola Nicolici, Jason Thong, N. Nicolici, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Hardware/Software Co-testing of Embedded Memories in Complex SOCs

Qiang Xu, Nicola Nicolici, Bai Hong Fang, 2003, ICCAD 2003.

Embedded compact deterministic test for IP-protected cores

Nicola Nicolici, Adam B. Kinsman, Jonathan I. Hewitt, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding

Nicola Nicolici, Adam B. Kinsman, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging

Nicola Nicolici, Ho Fai Ko, 2012, IEEE Transactions on Computers.

On reducing wrapper boundary register cells in modular soc testing

Qiang Xu, Nicola Nicolici, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

On Bypassing Blocking Bugs during Post-Silicon Validation

Nicola Nicolici, Ehab Anis Daoud, 2008, 2008 13th European Test Symposium.

Testability Trade-Offs for BIST Data Paths

Bashir M. Al-Hashimi, Nicola Nicolici, 2004, J. Electron. Test..

Wrapper design for testing IP cores with multiple clock domains

Qiang Xu, Nicola Nicolici, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning

Nicola Nicolici, Zahra Lak, 2014, IEEE Transactions on Computers.

Automated trace signals selection using the RTL descriptions

Nicola Nicolici, Ho Fai Ko, 2010, 2010 IEEE International Test Conference.

Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types

Nicola Nicolici, Adam B. Kinsman, 2011, IEEE Transactions on Computers.