Lucas Antunes Tambara

Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs

Luca Sterpone, Fernanda Lima Kastensmidt, Jimmy Tarrillo, 2016 .

Neutron-Induced Single Event Effect in Mixed-Signal Flash-Based FPGA

Marcelo Lubaszewski, Tiago R. Balen, Fernanda Lima Kastensmidt, 2016 .

Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors

Fernanda Gusmão de Lima Kastensmidt, Lucas Antunes Tambara, Ádria Barros de Oliveira, 2017, 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS).

Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA

Fernanda Gusmão de Lima Kastensmidt, Lucas Antunes Tambara, André Flores dos Santos, 2017, 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS).

NANOSATC-BR – Subsystems and Payload

Nelson Jorge Schuch, Otavio Durao, Lucas Lopes Costa, 2009 .

Dynamic heavy ions SEE testing of NanoXplore radiation hardened SRAM-based FPGA: Reliability-performance analysis

Fernanda Lima Kastensmidt, Gennaro S. Rodrigues, Fabio Benevenuti, 2019 .

Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC

Fernanda Gusmão de Lima Kastensmidt, Lucas Antunes Tambara, Ádria Barros de Oliveira, 2017, ARC.

Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs

Fernanda Gusmão de Lima Kastensmidt, Jorge Tonfat, Fabio Benevenuti, 2017, ARC.