Gordon R. Chiu

An OpenCL™ Deep Learning Accelerator on Arria 10

Andrew C. Ling, Utku Aydonat, Shane O'Connell, 2017, FPGA.

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow

Stephen Dean Brown, Valavan Manohararajah, Deshanand P. Singh, 2006, SLIP '06.

Creating High Performance Applications with Intel's FPGA OpenCL™ SDK

Andrew C. Ling, Utku Aydonat, Shane O'Connell, 2017, IWOCL.

Flexibility: FPGAs and CAD in Deep Learning Acceleration

Mohamed S. Abdelfattah, Andrew C. Ling, Davor Capalija, 2018, ISPD.

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

Stephen Dean Brown, Valavan Manohararajah, Deshanand P. Singh, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs

Stephen Dean Brown, Valavan Manohararajah, Deshanand P. Singh, 2006, ICCAD.

Harnessing Numerical Flexibility for Deep Learning on FPGAs

Mohamed S. Abdelfattah, David Han, Andrew C. Ling, 2018, HEART.

The Stratix™ 10 Highly Pipelined FPGA Architecture

Valavan Manohararajah, David M. Lewis, David R. Galloway, 2016, FPGA.

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration

Mohamed S. Abdelfattah, Andrew C. Ling, Roberto DiCecco, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Mapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGAs

Deshanand P. Singh, Gordon R. Chiu, G.R. Chiu, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.