Fukashi Morishita

发表

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

Masaki Tsukude, Shigehiro Kuge, Fukashi Morishita, 1996 .

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

Hans Jürgen Mattausch, Kazutami Arimoto, Katsumi Dosaka, 2006, IEICE Trans. Electron..

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform

Kazutami Arimoto, Katsumi Dosaka, Fukashi Morishita, 2009, IEICE Trans. Electron..

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI

Isamu Hayashi, Kazutami Arimoto, Tetsushi Tanizaki, 2006, IEEE Custom Integrated Circuits Conference 2006.

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)

Hideto Hidaka, Katsuhiro Suma, Kazuyasu Fujishima, 1996 .

Dynamic floating body control SOI CMOS circuits for power managed multimedia ULSIs

Fukashi Morishita, K. Arimoto, M. Tsukude, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI

Isamu Hayashi, Kazutami Arimoto, Katsumi Dosaka, 2007, IEICE Trans. Electron..

A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit

Fukashi Morishita, Kazuhiro Ueda, Shunsuke Okura, 2015, IEEE Journal of Solid-State Circuits.

Semiconductor memory device with Ladungsableiteeinrichtung

Fukashi Morishita, Shigeki Tomishima, K. Arimoto, 1996 .

A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller

Isamu Hayashi, Kazuyasu Fujishima, Takeshi Fujino, 2002 .

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design

Isamu Hayashi, Kazutami Arimoto, Katsumi Dosaka, 2006, IEICE Trans. Electron..

A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform

Kazutami Arimoto, Katsumi Dosaka, Fukashi Morishita, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM

Fukashi Morishita, Kazutami Arimoto, Toshiyuki Oashi, 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system

Fukashi Morishita, Tsutomu Yoshihara, Okura Shunsuke, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM

Kazutami Arimoto, Katsumi Dosaka, Hideyuki Noda, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

A capacitorless twin-transistor random access memory (TTRAM) on SOI

Kazutami Arimoto, Katsumi Dosaka, Hideyuki Noda, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

CMOS SOI Memory Design Technology

Kazutami Arimoto, Fukashi Morishita, Kazutami Arimoto, 2008 .

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System

Kazutami Arimoto, Fukashi Morishita, Kazuhiro Ueda, 2013, IEEE Journal of Solid-State Circuits.

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)

Fukashi Morishita, Kazutami Arimoto, Michihiro Yamada, 1999 .

A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit

Fukashi Morishita, Kazuhiro Ueda, Shunsuke Okura, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Signal Management and Enhanced-on-Chip Tester

Yoshihiro Nagura, Katsuya Furue, Katsumi Dosaka, 2001 .

High efficiency Autonomous Controlled Cascaded LDOs for Green Battery system

Fukashi Morishita, Kazutami Arimoto, Tsutomu Yoshihara, 2009, 2009 IEEE 8th International Conference on ASIC.

A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform

Kazutami Arimoto, Fukashi Morishita, Katsumi Dosaka, 2006 .

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros

Kazutami Arimoto, Katsumi Dosaka, Teruhiko Amano, 2005, IEICE Trans. Electron..

A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems

Fukashi Morishita, Hiroyuki Kondo, Mitsuru Hiraki, 2021, 2021 Symposium on VLSI Circuits.

A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator

Fukashi Morishita, Norihito Kato, Wataru Saito, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).