W. Shen

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Jing-Yang Jou, Wen-Zen Shen, Juinn-Dar Huang, 1996, Proceedings of International Conference on Computer Aided Design.

My-box representation for faulty CMOS circuits

Chung Len Lee, Jung-Sheng Chen, Wen Zen Shen, 1990 .

The design of a systolic array system for linear state equations

C.-W. Jen, W.-Z. Shen, S.-J. Jou, 1988, [1988] Proceedings. International Conference on Systolic Arrays.

EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATOR

Shyh-Jye Jou, Wen Zen Shen, Y.-S. Tao, 1993 .

An event-driven incremental timing fault simulator

Shyh-Jye Jou, Wen Zen Shen, Shwu-Huey Chiou, 1991, 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers.

MOTA: a MOSFET timing simulator

Shyh-Jye Jou, Wen-Zen Shen, Chih-Wei Jen, 1986 .