Tsuyoshi Fujinaga

PAPER Special Section on Circuits and Design Techniques for Advanced Large Scale Integration VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition ∗

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kazuo Miura, 2011 .

A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kazuo Miura, 2009, INTERSPEECH.

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition

Masahiko Yoshimoto, Hiroshi Kawaguchi, Kazuo Miura, 2011, IEICE Trans. Electron..

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, IEEE Trans. Circuits Syst. I Regul. Pap..

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, IEICE Trans. Electron..

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.