Dimitrios Velenis

发表

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty

Marios C. Papaefthymiou, Eby G. Friedman, Dimitrios Velenis, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Processing active devices on Si interposer and impact on cost

Eric Beyne, Erik Jan Marinissen, Mirko Scholz, 2015, 2015 International 3D Systems Integration Conference (3DIC).

3D integration: Circuit design, test, and reliability challenges

Paul Marchal, Erik Jan Marinissen, Dimitrios Velenis, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees

Dimitrios Velenis, Boyan Semerdjiev, 2007, 2007 IEEE International Symposium on Circuits and Systems.

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking

Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis, 2010, 2010 15th IEEE European Test Symposium.

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Luca Benini, Federico Angiolini, Paresh Limaye, 2010, IEEE Journal of Solid-State Circuits.

Design issues and considerations for low-cost 3D TSV IC technology

Paresh Limaye, Bart Vandevelde, Eric Beyne, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Demonstration of Speed and Power Enhancements through Application of Non-Zero Clock Skew Scheduling

Eby G. Friedman, Dimitrios Velenis, Kevin T. Tang, 2000 .

Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees

Dimitrios Velenis, Boyan Semerdjiev, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Buffer sizing for delay uncertainty induced by process variations

Eby G. Friedman, Dimitrios Velenis, Ramyashree Sundaresha, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Development of cost-effective biocompatible packaging for microelectronic devices

Paolo Fiorini, Chris Van Hoof, Dimitrios Velenis, 2011, 2011 Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

Effects of process and environmental variations on timing characteristics of clocked registers

Dimitrios Velenis, William R. Roberts, 2006, GLSVLSI '06.

Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers

Dimitrios Velenis, William R. Roberts, 2005, PATMOS.

Power supply variation effects on timing characteristics of clocked registers

Dimitrios Velenis, William R. Roberts, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Active-lite interposer for 2.5 & 3D integration

Eric Beyne, Erik Jan Marinissen, Mirko Scholz, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling

Eby G. Friedman, Dimitrios Velenis, Kevin T. Tang, 2002, J. Circuits Syst. Comput..

Effects of parameter variations on timing characteristics of clocked registers

Dimitrios Velenis, William R. Roberts, 2005, 2005 IEEE International Conference on Electro Information Technology.

SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links

Basil S. Maglaris, Dimitrios Velenis, Dimitrios Kalogeras, 2002, NETWORKING.

Effects of crosstalk noise on H-tree clock distribution networks

Dimitrios Velenis, Itisha Chanodia, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Effects of parameter variations and crosstalk noise on H-tree clock distribution networks

Dimitrios Velenis, Itisha Chanodia, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Cost effectiveness of 3D integration options

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Clock tree layout design for reduced delay uncertainty

Marios C. Papaefthymiou, Eby G. Friedman, Dimitrios Velenis, 2004, IEEE International SOC Conference, 2004. Proceedings..

Impact of 3D design choices on manufacturing cost

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2009, 2009 IEEE International Conference on 3D System Integration.

Si interposer build-up options and impact on 3D system cost

Eric Beyne, Erik Jan Marinissen, Dimitrios Velenis, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

3D stacking using ultra thin dies

Eric Beyne, Dimitrios Velenis, Mikael Detalle, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Buffer Sizing for Crosstalk Induced Delay Uncertainty

Eby G. Friedman, Dimitrios Velenis, 2004, PATMOS.

Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static $C$–$V$ Technique

Dimitrios Velenis, Guruprasad Katti, Michele Stucchi, 2012, IEEE Transactions on Instrumentation and Measurement.

A High-Bandwidth Fine-Pitch 2.57Tbps/mm In-package Communication Link Achieving 48fJ/bit/mm Efficiency

Eric Beyne, Dimitrios Velenis, Marian Verhelst, 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

Reduced delay uncertainty in high performance clock distribution networks

Marios C. Papaefthymiou, Eby G. Friedman, Dimitrios Velenis, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.