Zwei-Mei Lee

Correction to "A Third-Order Modulator in 0.18- m CMOS With Calibrated Mixed-Mode Integrators"

Hung-Chih Liu, Jieh-Tsorng Wu, J. H. Shim, 2005 .

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

Jieh-Tsorng Wu, Cheng-Yeh Wang, Zwei-Mei Lee, 2007, IEEE J. Solid State Circuits.

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

Hung-Chih Liu, Jieh-Tsorng Wu, Zwei-Mei Lee, 2005 .

A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration

Hung-Chih Liu, Jieh-Tsorng Wu, Zwei-Mei Lee, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

Correction to “ A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration”

Hung-Chih Liu, Jieh-Tsorng Wu, Zwei-Mei Lee, 2005 .

A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

Ping Chen, Zwei-Mei Lee, Jui-Yuan Tsai, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS

Chun-Geik Tan, Osama Shana'a, Zwei-Mei Lee, 2013, IEEE Journal of Solid-State Circuits.

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

Jieh-Tsorng Wu, Cheng-Yeh Wang, Zwei-Mei Lee, 2006, IEEE Journal of Solid-State Circuits.

A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application

Chen-Yen Ho, Sheng-Jui Huang, Zwei-Mei Lee, 2011, IEEE Asian Solid-State Circuits Conference 2011.

A digital background calibration technique for pipelined analog-to-digital converters

Hung-Chih Liu, Jieh-Tsorng Wu, Zwei-Mei Lee, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..