Ku-Feng Lin

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

Meng-Fan Chang, Shu-Meng Yang, Che-Wei Wu, 2012, 2012 IEEE International Solid-State Circuits Conference.

A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process

Y. Chih, Chieh-Pu Lo, H. Chuang, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

Meng-Fan Chang, Heng-Yuan Lee, Yu-Sheng Chen, 2013, IEEE Journal of Solid-State Circuits.

Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Meng-Fan Chang, Yen-Chen Liu, Yu-Der Chih, 2015, IEEE Journal of Solid-State Circuits.

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Heng-Yuan Lee, Frederick T. Chen, Ming-Jinn Tsai, 2011, 2011 IEEE International Solid-State Circuits Conference.

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Meng-Fan Chang, Sreedhar Natarajan, Yu-Der Chih, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).