Sriram Vajapeyam

发表

On the instruction-level characteristics of scalar code in highly-vectorized scientific applications

Sriram Vajapeyam, Wei-Chung Hsu, 1992, MICRO 1992.

Non-strict cache coherence: exploiting data-race tolerance in emerging applications

Sriram Vajapeyam, Siddhartha V. Tambat, S. Vajapeyam, 2000, Proceedings 2000 International Conference on Parallel Processing.

Proceedings of the 8th International Conference on High Performance Computing

Viktor K. Prasanna, Sriram Vajapeyam, Burkhard Monien, 2001 .

Trace Processors: Moving to Fourth-Generation Microarchitectures

James E. Smith, Sriram Vajapeyam, James E. Smith, 1997, Computer.

Sub-tagged Caches: Study of Variable Cache-Block Size Emulation

Sriram Vajapeyam, Siddhartha V. Tambat, S. Muthulaxmi, 2001 .

Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences

Tulika Mitra, Sriram Vajapeyam, 1997, ISCA.

Instruction-level characterization of the Cray Y-MP processor

Sriram Vajapeyam, 1992 .

Dynamic vectorization: a mechanism for exploiting far-flung ILP in ordinary programs

Tulika Mitra, Sriram Vajapeyam, P. J. Joseph, 1999, ISCA.

Tradeoffs in instruction format design for horizontal architectures

Gurindar S. Sohi, Sriram Vajapeyam, G. Sohi, 1989, ASPLOS III.

Page-Level Behavior of Cache Contention

Sriram Vajapeyam, Siddhartha V. Tambat, 2002, IEEE Computer Architecture Letters.

Instruction issue logic for high-performance, interruptable pipelined processors

Gurindar S. Sohi, Sriram Vajapeyam, G. Sohi, 1987, ISCA '87.

Toward Effective Scalar Hardware for Highly Vectorizable Applications

Sriram Vajapeyam, Wei-Chung Hsu, 1993, J. Parallel Distributed Comput..

On the instruction-level characteristics of scalar code in highly-vectorized scientific applications

Sriram Vajapeyam, Wei-Chung Hsu, 1992, MICRO.

High Performance Computing — HiPC 2001

Viktor K. Prasanna, Sriram Vajapeyam, Burkhard Monien, 2001, Lecture Notes in Computer Science.

Proceedings of the 7th International Conference on High Performance Computing

Viktor K. Prasanna, Mateo Valero, Sriram Vajapeyam, 2000 .

Instruction issue logic for high-performance, interruptable pipelined processors

Gurindar S. Sohi, Sriram Vajapeyam, G. Sohi, 1987, ISCA '98.

Experience With Crystal, Charlotte and Lynx - Third Report

Sriram Vajapeyam, Raphael A. Finkel, Mukesh Kacker, 1986 .

Early 21st Century Processors - Guest Editors' Introduction

Mateo Valero, Sriram Vajapeyam, 2001, Computer.

Understanding Shannon's Entropy metric for Information pdf

Sriram Vajapeyam, S. Vajapeyam, 2014, ArXiv.

High Performance Computing — HiPC 2000

Viktor K. Prasanna, Mateo Valero, Sriram Vajapeyam, 2001, Lecture Notes in Computer Science.

Program-level control of network delay for parallel asynchronous iterative applications

Sriram Vajapeyam, P. J. Joseph, 1996, Proceedings of 3rd International Conference on High Performance Computing (HiPC).

High performance computing, HiPC 2003 : 10th International Conference, Hyderabad, India, December 17-20, 2003 : proceedings

Sriram Vajapeyam, Burkhard Monien, V. K. Prasanna Kumar, 2001 .

An empirical study of the CRAY Y-MP processor using the PERFECT club benchmarks

Gurindar S. Sohi, Sriram Vajapeyam, Wei-Chung Hsu, 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.

Load balancing in a heterogeneous computing environment

Sriram Vajapeyam, Sridhar Gopal, S. Vajapeyam, 1998, Proceedings of the Thirty-First Hawaii International Conference on System Sciences.

An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks

Gurindar S. Sohi, Sriram Vajapeyam, Wei-Chung Hsu, 1991, ISCA.

Tradeoffs in instruction format design for horizontal architectures

Gurindar S. Sohi, Sriram Vajapeyam, 1989, ASPLOS 1989.

Whither Indian Computer Science R & D?

Sriram Vajapeyam, 1999, HiPC.

Early 21 st Century Processors

Mateo Valero, Sriram Vajapeyam, 2001 .