T. S. Barnett

High-Value Design Techniques for Mitigating Random Defect Sensitivities

D.N. Maynard, T.S. Barnett, R.J. Rosner, 2008, IEEE Transactions on Semiconductor Manufacturing.

Extending integrated-circuit yield-models to estimate early-life reliability

Adit D. Singh, Victor P. Nelson, Thomas S. Barnett, 2003, IEEE Trans. Reliab..

Relating yield models to burn-in fall-out in time

Adit D. Singh, Thomas S. Barnett, A. Singh, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Redundancy implications for early-life reliability: experimental verification of an integrated yield-reliability model

Adit D. Singh, Matt Grady, Kathleen G. Purdy, 2002, Proceedings. International Test Conference.

Yield-reliability modeling: experimental verification and application to burn-in reduction

Adit D. Singh, Matt Grady, Kathleen G. Purdy, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).