Vikram Suresh

发表

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, IEEE Journal of Solid-State Circuits.

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

Ultra-low energy circuit building blocks for security technologies

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2017, IEEE Journal of Solid-State Circuits.

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2016, IEEE Journal of Solid-State Circuits.

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

Invited paper: Ultra-low energy security circuit primitives for IoT platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2020, 2020 IEEE Symposium on VLSI Circuits.

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

Design of 8T-nanowire RAM array

Vikram Suresh, Csaba Andras Moritz, Mostafizur Rahman, 2013, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

250mV–950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

Ultra-low energy security circuits for IoT applications

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

Guarding Machine Learning Hardware Against Physical Side-channel Attacks pdf

Vikram Suresh, Rosario Cammarota, Aydin Aysu, 2021, ACM J. Emerg. Technol. Comput. Syst..

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2021, IEEE Journal of Solid-State Circuits.