Himanshu Kaul

发表

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, IEEE Journal of Solid-State Circuits.

A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect

David Blaauw, Himanshu Kaul, Ram Krishnamurthy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 32nm 8.3GHz 64-entry × 32b variation tolerant near-threshold voltage register file

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2013, IEEE Journal of Solid-State Circuits.

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

A novel buffer circuit for energy efficient signaling in dual-VDD systems

Himanshu Kaul, Dennis Sylvester, D. Sylvester, 2005, ACM Great Lakes Symposium on VLSI.

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

Active shielding of RLC global interconnects

David Blaauw, Himanshu Kaul, Dennis Sylvester, 2002, TAU '02.

Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses

Mark Anders, Himanshu Kaul, Ram Krishnamurthy, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Power-aware global signaling strategies

Himanshu Kaul, Sani R. Nassif, Dennis Sylvester, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

A 2.9–33.0 TOPS/W Reconfigurable 1-D/2-D Compute-Near-Memory Inference Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Future performance challenges in nanometer design

Himanshu Kaul, Dennis Sylvester, D. Sylvester, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2011, IEEE Journal of Solid-State Circuits.

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2009, IEEE Journal of Solid-State Circuits.

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2017, IEEE Journal of Solid-State Circuits.

53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections

Mark Anders, Himanshu Kaul, Ram Krishnamurthy, 2011, Low Power Networks-on-Chip.

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2016, IEEE Journal of Solid-State Circuits.

Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators

Sanu Mathew, Mark Anders, Himanshu Kaul, 2019, 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH).

A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects

Mark Anders, Himanshu Kaul, Ram Krishnamurthy, 2006, 2006 IEEE International SOC Conference.

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS

Himanshu Kaul, Amit Agarwal, Shekhar Borkar, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS

Himanshu Kaul, 2005, Proceedings 2005 IEEE International SOC Conference.

MetaXplorer: an intelligent and adaptable metasearch engine using a novel ordered weighted averaging operator

Himanshu Kaul, Daya Gupta, Neha Dimri, 2018, Int. J. Syst. Assur. Eng. Manag..

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

DVS for on-chip bus designs based on timing error correction

David Blaauw, Himanshu Kaul, Trevor N. Mudge, 2005, Design, Automation and Test in Europe.

Low-power on-chip communication based on transition-aware global signaling (TAGS)

Himanshu Kaul, Dennis Sylvester, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Power-Driven Challenges in Nanometer Design

Himanshu Kaul, Dennis Sylvester, 2001, IEEE Des. Test Comput..

A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2013, IEEE Journal of Solid-State Circuits.

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2020, 2020 IEEE Symposium on VLSI Circuits.

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 350mV–900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications

Mark Anders, Himanshu Kaul, Amit Agarwal, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, IEEE Journal of Solid-State Circuits.

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

250mV–950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A robust edge encoding technique for energy-efficient multi-cycle interconnect

David Blaauw, Himanshu Kaul, Ram Krishnamurthy, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses

Mark Anders, Himanshu Kaul, Ram Krishnamurthy, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Active shields: a new approach to shielding global wires

David Blaauw, Himanshu Kaul, Dennis Sylvester, 2002, GLSVLSI '02.

Investigating biocomplexity through the agent-based paradigm

Himanshu Kaul, Yiannis Ventikos, Y. Ventikos, 2013, Briefings Bioinform..

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2021, IEEE Journal of Solid-State Circuits.

Performance optimization of critical nets through active shielding

David Blaauw, Himanshu Kaul, Dennis Sylvester, 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Himanshu Kaul, Amit Agarwal, Ram Krishnamurthy, 2012, IEEE Journal of Solid-State Circuits.

A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A Dual-Supply 4GHz 13fJ/bit/search 64×128b CAM in 65nm CMOS

Himanshu Kaul, A. Agarwal, R.K. Krishnamurthy, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2021, IEEE Journal of Solid-State Circuits.