Steven Hsu

发表

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, IEEE Journal of Solid-State Circuits.

A 32nm 8.3GHz 64-entry × 32b variation tolerant near-threshold voltage register file

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2013, IEEE Journal of Solid-State Circuits.

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

Kaushik Roy, Steven Hsu, Ram Krishnamurthy, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Dynamic addressing memory arrays with physical locality

Steven Hsu, Ram Krishnamurthy, Shih-Lien Lu, 2002, MICRO.

A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

An improved unified scalable radix-2 Montgomery multiplier

Sanu Mathew, Mark Anders, Steven Hsu, 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2011, IEEE Journal of Solid-State Circuits.

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2009, IEEE Journal of Solid-State Circuits.

Self calibrating circuit design for variation tolerant VLSI systems

Kaushik Roy, Steven Hsu, Ram Krishnamurthy, 2005, 11th IEEE International On-Line Testing Symposium.

A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS

Sanu Mathew, Mark Anders, Steven Hsu, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

Steven Hsu, Ram Krishnamurthy, Shekhar Y. Borkar, 2003, ISLPED '03.

Near-threshold voltage (NTV) design — Opportunities and challenges

Mark Anders, Amit Agarwal, Steven Hsu, 2012, DAC Design Automation Conference 2012.

A brick wall, a locked door, and a bandit: a physical security metaphor for firewall warnings

Steven Hsu, Kirstie Hawkey, Konstantin Beznosov, 2011, SOUPS.

A simple and practical approach for building lithography simulation models using a limited set of CD data and SEM pictures

Yan Wang, Steven Hsu, Benjamin Lin, 2007, SPIE Advanced Lithography.

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS

Sanu Mathew, Vikram Suresh, Mark Anders, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS

Kaushik Roy, Amit Agarwal, Steven Hsu, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2013, IEEE Journal of Solid-State Circuits.

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 350mV–900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications

Mark Anders, Himanshu Kaul, Amit Agarwal, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, IEEE Journal of Solid-State Circuits.

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

250mV–950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2019, 2019 Symposium on VLSI Circuits.

A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS

Sanu Mathew, Mark Anders, Steven Hsu, 2007, 2007 IEEE International SOC Conference.

Promoting a physical security mental model for personal firewall warnings

Steven Hsu, Kirstie Hawkey, Konstantin Beznosov, 2011, CHI Extended Abstracts.

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

Amit Agarwal, Steven Hsu, Ram Krishnamurthy, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.