S.Z. Chang

A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications

K.Y. Lee, J.Y.C. Sun, K.L. Young, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applications

S.Z. Chang, B.L. Lin, J.J. Liaw, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

S. Van Elshocht, P. Lehnen, C. Vrancken, 2007, 2007 IEEE Symposium on VLSI Technology.