Tsukasa Shirotori

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode

Tetsuya Iizuka, Takayasu Sakurai, M. Isobe, 1988 .

A 32 kbyte integrated cache memory

Kenji Maeguchi, Takayasu Sakurai, Akio Miyoshi, 1989 .

A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture

Yukihiro Fujimoto, Kazutaka Nogami, Tsukasa Shirotori, 1993 .

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC

Sumio Tanaka, Tetsuya Iizuka, Takayasu Sakurai, 1990 .

A 0.5W 64kB Snoopy Cache Memory With Flexible Expandability

Yukihiro Fujimoto, Kazutaka Nogami, Kiyoshi Kobayashi, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A semiconductor device having a logic circuit and a memory

Tsukasa Shirotori, Kazuhiro C O Patent Div Sawada, Takayasu C O Patent Di Sakurai, 1989 .

h?=-I Data Streaming Cache

Takayasu Sakurai, Yasuo Unekawa, Yukihiro Fujimoto, 1994 .

A 110-MHz/1-Mb synchronous TagRAM

Takayasu Sakurai, Yasuo Unekawa, Yukihiro Fujimoto, 1994 .

A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation

Yukihiro Fujimoto, Kiyoshi Kobayashi, Kazutaka Nogami, 1991 .

Architecture and Design Methodology of 32KByte Integrated Cache Memory

Tetsuya Iizuka, Kenji Maeguchi, Takayasu Sakurai, 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.