Takahiro Deguchi

A Timing-Driven Hierarchical Global Routing Method with Buffer-Insertion and Wire-Sizing for Multi-Layer ULSI

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 1999 .

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

A performance-driven global routing algorithm with wire-sizing and buffer-insertion

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 2000, ASP-DAC '00.