J. Kye

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

A. Wei, J. Singh, G. Bouche, 2014, 2014 IEEE International Electron Devices Meeting.

Innovations in special constructs for standard cell libraries in sub 28nm technologies

R. Augur, J. Kye, M. Rashed, 2013, 2013 IEEE International Electron Devices Meeting.

Patterning of Sub-0.18mm Logic Gates with Phase-Edge PSM

J. Kye, H. Kang, D. Cha, 1998 .