C. Bieser

Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs

Klaus D. Müller-Glaser, Carsten Bieser, K. Müller-Glaser, 2006, Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06).

Hardware/software co-training lab: from VHDL bit-level coding up to CASE-Tool based system modeling

Klaus D. Müller-Glaser, Jürgen Becker, Carsten Bieser, 2005, 2005 IEEE International Conference on Microelectronic Systems Education (MSE'05).

Xilinx Virtex-II FPGA Design Acceleration Using a Novel Merging Methodology for Partial Configuration Bitstreams

C. Bieser, K.-D. Mueller-Glaser, K. Mueller-Glaser, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.