Zaid Al-Ars

发表

Designmap: capturing design knowledge in architectural practice

EB Tuncer, Zaid Al-Ars, E Akar, 2006 .

Automating defects simulation and fault modeling for SRAMs

Paolo Prinetto, Stefano Di Carlo, Zaid Al-Ars, 2008, 2008 IEEE International High Level Design Validation and Test Workshop.

Testing static and dynamic faults in random access memories

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Calculation of worst-case execution time for multicore processors using deterministic execution

Hamid Mushtaq, Zaid Al-Ars, Koen Bertels, 2015, 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs

Ad J. van de Goor, Zaid Al-Ars, 2003, IEEE Trans. Computers.

Impact of memory cell array bridges on the faulty behavior in embedded DRAMs

Ad J. van de Goor, Zaid Al-Ars, 2000, Proceedings of the Ninth Asian Test Symposium.

The effectiveness of the scan test and its new variants

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

Fault Diagnosis Using Test Primitives in Random Access Memories

Said Hamdioui, Zaid Al-Ars, 2009, 2009 Asian Test Symposium.

An Overview of Federated Deep Learning Privacy Attacks and Defensive Strategies pdf

Zaid Al-Ars, David Enthoven, Z. Al-Ars, 2020, Federated Learning Systems.

Test generation and optimization for DRAM cell defects using electrical simulation

Ad J. van de Goor, Zaid Al-Ars, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths

Ernst Houtgast, Vlad Mihai Sima, Zaid Al-Ars, 2018, Comput. Biol. Chem..

March SL: a test for all static linked memory faults

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2003, 2003 Test Symposium.

Quines are the Fittest Programs - Large Nesting Algorithmic Probability Converges to Constructors

Zaid Al-Ars, Aritra Sarkar, Koen Bertels, 2020 .

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor, 2009, 2009 Asian Test Symposium.

Work-in-Progress: A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

Jan Hidders, Zaid Al-Ars, Jian Fang, 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Impact of stresses on the fault coverage of memory tests

Said Hamdioui, Ad J. van de Goor, Rob Wadsworth, 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

High performance and resource efficient biological sequence alignment

Zaid Al-Ars, Mottaqiallah Taouil, Laiq Hasan, 2010, 2010 Annual International Conference of the IEEE Engineering in Medicine and Biology.

Testing for Parasitic Memory Effect in SRAMs

Said Hamdioui, Zaid Al-Ars, Claude Thibeault, 2011, 2011 Asian Test Symposium.

Influence of parasitic memory effect on single-cell faults in SRAMs

Michel Renovell, Said Hamdioui, Zaid Al-Ars, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

PPM Reduction on Embedded Memories in System on Chip

Said Hamdioui, Zaid Al-Ars, Javier Jiménez, 2007, 12th IEEE European Test Symposium (ETS'07).

BrainFrame: A heterogeneous accelerator platform for neuron simulations

Georgios Smaragdos, Christos Strydis, Ioannis Sourdis, 2016 .

Manifestation of Precharge Faults in High Speed DRAM Devices

Said Hamdioui, Georgi Gaydadjiev, Zaid Al-Ars, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Influence of bit line twisting on the faulty behavior of DRAMs

Ad J. van de Goor, Zaid Al-Ars, Martin Herzog, 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

Detecting memory faults in the presence of bit line coupling in SRAM devices

Said Hamdioui, Zaid Al-Ars, Sandra Irobi, 2010, 2010 IEEE International Test Conference.

Non-algorithmic stress optimization using simulation for DRAMs

Said Hamdioui, Zaid Al-Ars, 2009, 2009 4th International Design and Test Workshop (IDT).

Framework for fault analysis and test generation in DRAMs

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2005, Design, Automation and Test in Europe.

DRAM specific approximation of the faulty behavior of cell defects

Ad J. van de Goor, Zaid Al-Ars, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Diminished-1 Fermat Number Transform for Integer Convolutional Neural Networks

Nauman Ahmed, Zaid Al-Ars, Koen Bertels, 2019, 2019 IEEE 4th International Conference on Big Data Analytics (ICBDA).

Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs

Said Hamdioui, Zaid Al-Ars, Sandra Irobi, 2011, 2011 Sixteenth IEEE European Test Symposium.

Effects of bit line coupling on the faulty behavior of DRAMs

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Approximating infinite dynamic behavior for DRAM cell defects

Ad J. van de Goor, Zaid Al-Ars, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

The effectiveness of the scan test and its new variants

Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, 2004 .

Linked faults in random access memories: concept, fault models, test algorithms, and industrial results

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2008, 2008 IEEE International Test Conference.

Using VLIW softcore processors for image processing applications

Stephan Wong, Zaid Al-Ars, Joost Hoozemans, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

SparkJNI: A Toolchain for Hardware Accelerated Big Data Apache Spark

Zaid Al-Ars, Tudor Alexandru Voicu, 2019, 2019 IEEE 4th International Conference on Big Data Analytics (ICBDA).

DOPA: GPU-based protein alignment using database and memory access optimizations

Zaid Al-Ars, Laiq Hasan, Marijn Kentie, 2011, BMC Research Notes.

DRAM fault analysis and test generation

Zaid Al-Ars, 2005 .

Heterogeneous hardware accelerators interconnect: An overview

Zaid Al-Ars, Cuong Pham-Quoc, Koen Bertels, 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach

Said Hamdioui, Zaid Al-Ars, Jörg E. Vollrath, 2005, 14th Asian Test Symposium (ATS'05).

Cluster-based Apache Spark implementation of the GATK DNA analysis pipeline

Hamid Mushtaq, Zaid Al-Ars, Z. Al-Ars, 2015, 2015 IEEE International Conference on Bioinformatics and Biomedicine (BIBM).

Soft faults and the importance of stresses in memory testing

Ad J. van de Goor, Zaid Al-Ars, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Analyzing the impact of process variations on DRAM testing using border resistance traces

Ad J. van de Goor, Zaid Al-Ars, 2003, 2003 Test Symposium.

Systematic memory test generation for DRAM defects causing two floating nodes

Ad J. van de Goor, Zaid Al-Ars, 2003, Records of the 2003 International Workshop on Memory Technology, Design and Testing.

DRAM-Specific Space of Memory Tests

Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor, 2006, 2006 IEEE International Test Conference.

Optimizing stresses for testing DRAM cell defects using electrical simulation

Ad J. van de Goor, Zaid Al-Ars, Detlev Richter, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Tests for address decoder delay faults in RAMs due to inter-gate opens

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Scan more with memory scan test

Said Hamdioui, Zaid Al-Ars, Z. Al-Ars, 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs

Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modeling techniques and tests for partial faults in memory devices

Ad J. van de Goor, Zaid Al-Ars, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Space of DRAM Fault Models and Corresponding Testing

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A memory specific notation for fault modeling

Ad J. van de Goor, Zaid Al-Ars, Detlev Richter, 2001, Proceedings 10th Asian Test Symposium.

Optimizing Test Length for Soft Faults in DRAM Devices

Said Hamdioui, Georgi Gaydadjiev, Zaid Al-Ars, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

CHOP: haplotype-aware path indexing in population graphs

Zaid Al-Ars, Jasper Linthorst, Henne Holstege, 2018, bioRxiv.

Test Set Development for Cache Memory in Modern Microprocessors

Stamatis Vassiliadis, Said Hamdioui, Georgi Gaydadjiev, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A New Test Paradigm for Semiconductor Memories in the Nano-Era

Said Hamdioui, Zaid Al-Ars, Sandra Irobi, 2011, 2011 Asian Test Symposium.

An Overview of Hardware-Based Acceleration of Biological Sequence Alignment

Zaid Al-Ars, Laiq Hasan, Z. Al-Ars, 2011 .

Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs

Zaid Al-Ars, A. J. van de Goor, Detlev Richter, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis

Vlad Mihai Sima, Zaid Al-Ars, Shanshan Ren, 2015, 2015 IEEE International Conference on Bioinformatics and Biomedicine (BIBM).

An efficient and high performance linear recursive variable expansion implementation of the smith-waterman algorithm

Zaid Al-Ars, Laiq Hasan, 2009, 2009 Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

Transient faults in DRAMs: concept, analysis and impact on tests

Ad J. van de Goor, Zaid Al-Ars, 2001, Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing.

An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

Ernst Houtgast, Vlad Mihai Sima, Zaid Al-Ars, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

Opens and Delay Faults in CMOS RAM Address Decoders

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2006, IEEE Transactions on Computers.

A fault primitive based analysis of linked faults in RAMs

Said Hamdioui, Ad J. van de Goor, Zaid Al-Ars, 2003, Records of the 2003 International Workshop on Memory Technology, Design and Testing.

Evaluation for intra-word faults in word-oriented RAMs

Said Hamdioui, Zaid Al-Ars, John Delos Reyes, 2004, 13th Asian Test Symposium.

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Ad J. van de Goor, Zaid Al-Ars, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.