M. B. Ghaznavi-Ghoushchi

发表

A new Chua’s circuit with monolithic Chua’s diode and its use for efficient true random number generation in CMOS 180 nm

H. Moqadasi, M. B. Ghaznavi-Ghoushchi, 2015 .

Two phase nonoverlapping clocked All-N-Logic in subthreshold region with 49fJ power delay product

M. B. Ghaznavi-Ghoushchi, M. Kargar, 2012, The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012).

A Low-Power CMOS Transceiver in 130 nm for Wireless Sensor Network Applications

M. B. Ghaznavi-Ghoushchi, A. R. Behrouj, A. R. Ghorbani, 2019, Wirel. Pers. Commun..

Design and implementation of a novel secure internet voting protocol using Java Card 3 technology

M. B. Ghaznavi-Ghoushchi, Mostafa Mohammadpourfard, Mohammad-Ali Doostari, 2014, Int. J. Bus. Inf. Syst..

Low rate DOS traceback based on sum of flows

M. B. Ghaznavi-Ghoushchi, M. Hamedi-Hamzehkolaie, M. J. Shamani, 2012, 6th International Symposium on Telecommunications (IST).

A power efficient multi-level output all digital LDO with fast settling time and built in self calibration for DVFS and multi-VDD applications

M. B. Ghaznavi-Ghoushchi, S. Kaedi, M. Rahimi, 2015, 2015 23rd Iranian Conference on Electrical Engineering.

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

M. B. Ghaznavi-Ghoushchi, Masoumeh Souri, 2016, Circuits Syst. Signal Process..

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

Jamshid Shanbehzadeh, M. B. Ghaznavi-Ghoushchi, Alireza Behrad, 2016, J. Electronic Imaging.

A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm

Mojtaba Lotfizad, M. B. Ghaznavi-Ghoushchi, Nasser Erfani Majd, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

An Improved Watchdog Technique Based On Power-Aware Hierarchical Design For Ids In Wireless Sensor Networks pdf

M. B. Ghaznavi-Ghoushchi, A. Forootaninia, 2012, ArXiv.

The xDotGrid native, cross-platform, high-performance xDFS file transfer framework pdf

M. B. Ghaznavi-Ghoushchi, Alireza Poshtkohi, M. Ghaznavi-Ghoushchi, 2012, Comput. Electr. Eng..

Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors

Ali Afzali-Kusha, M. B. Ghaznavi-Ghoushchi, Behzad Eghbalkhah, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation

M. B. Ghaznavi-Ghoushchi, Seyedeh Fatemeh Ghamkhari, 2014, Circuits Syst. Signal Process..

Performance improvement of differential static CMOS logic family

M. B. Ghaznavi-Ghoushchi, Zohreh Kiaee, 2011, 2011 IEEE EUROCON - International Conference on Computer as a Tool.

A new low power profile for mixed-signal design of SARADC in Wireless Sensor Network applications

M. B. Ghaznavi-Ghoushchi, S. Roshany, M. Ghaznavi-Ghoushchi, 2011, 2011 19th Iranian Conference on Electrical Engineering.

Attribute-based collaborative filtering using genetic algorithm and weighted C-means algorithm

Mojtaba Salehi, M. B. Ghaznavi-Ghoushchi, Isa Nakhai Kamal Abadi, 2013, Int. J. Bus. Inf. Syst..

An ultra low-power current-mode clock and data recovery design with input bit-rate adaptability for biomedical applications in CMOS 90 nm

M. B. Ghaznavi-Ghoushchi, J. Ahmadi-Farsani, H. Sadjedi, 2018, Integr..

Improvement of timing specifications in second order electronic systems using programmable CMOS Posicast pulse shapers

M. B. Ghaznavi-Ghoushchi, M. Rahimi, 2012, 20th Iranian Conference on Electrical Engineering (ICEE2012).

CSAM: A clock skew-aware aging mitigation technique

Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, 2015, Microelectron. Reliab..

A low-area, 43.5% PAE, 0.9 W, Class-E differential power amplifier in 2.4 GHz for IoT applications

M. B. Ghaznavi-Ghoushchi, A. R. Ghorbani, 2018, Integr..

A Novel Fully Differential CMOS Class-E Power Amplifier with Higher Output Power and Efficiency for IoT Application

M. B. Ghaznavi-Ghoushchi, A. R. Ghorbani, M. Ghaznavi-Ghoushchi, 2017, Wirel. Pers. Commun..

An effective recommendation framework for personal learning environments using a learner preference tree and a GA

Mojtaba Salehi, M. B. Ghaznavi-Ghoushchi, Isa Nakhai Kamal Abadi, 2013, IEEE Transactions on Learning Technologies.

An RRAM-based MLC design approach

M. B. Ghaznavi-Ghoushchi, A. A. Bagheri-Soulla, M. Ghaznavi-Ghoushchi, 2017, Microelectron. J..

An energy-efficient threshold voltage extractor with the burst-mode operation and extended long-term variations using FVF

M. B. Ghaznavi-Ghoushchi, A. R. Kariman, A. R. Shamshiri, 2020, Microelectron. J..

An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

Mojtaba Lotfizad, M. B. Ghaznavi-Ghoushchi, Nasser Erfani Majd, 2011, IEICE Electron. Express.

A new low-power, low-area, parallel prefix Sklansky adder with reduced inter-stage connections complexity

M. B. Ghaznavi-Ghoushchi, Mahta Moghaddam, 2011, 2011 IEEE EUROCON - International Conference on Computer as a Tool.

A new parallel prefix adder structure with efficient critical delay path and gradded bits efficiency in CMOS 90nm technology

H. Moqadasi, M. B. Ghaznavi-Ghoushchi, 2015, 2015 23rd Iranian Conference on Electrical Engineering.

A new secure Internet voting protocol using Java Card 3 technology and Java information flow concept

M. B. Ghaznavi-Ghoushchi, Mostafa Mohammadpourfard, Mohammad-Ali Doostari, 2015, Secur. Commun. Networks.

A high performance, race eliminated, two phase nonoverlapping clocked All-N-Logic for both strong and subthreshold designs

M. B. Ghaznavi-Ghoushchi, M. Kargar, 2012, The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012).

A 4.2GHz, 3.3mW, 1.1pJ, 90nm 64-bit new digital comparator with 1.2 clock pipeline delay

M. B. Ghaznavi-Ghoushchi, M. Larijani, 2011, 2011 19th Iranian Conference on Electrical Engineering.

Memristor based circuit design using charge and attached capacitor

M. B. Ghaznavi-Ghoushchi, A. A. Bagheri-Soulla, 2016, Microelectron. J..

Design of low-voltage shallow-depth differential source coupled logic using feedback and feedforward techniques

M. B. Ghaznavi-Ghoushchi, M. Rafiee, M. Rafiee, 2019, Microelectron. J..

NEMR: A Nonequidistant DPA Attack-Proof of Modular Reduction in a CRT Implementation of RSA

M. B. Ghaznavi-Ghoushchi, Mohammad-Ali Doostari, Saman Kaedi, 2018, J. Circuits Syst. Comput..

Energy-efficient secure distributed storage in mobile cloud computing

M. B. Ghaznavi-Ghoushchi, Amir Afianian, S. S. Nobakht, 2015, 2015 23rd Iranian Conference on Electrical Engineering.

An output node split CMOS logic for high-performance and large capacitive-load driving scenarios

M. B. Ghaznavi-Ghoushchi, M. Rafiee, 2018, Microelectron. J..

VLSI implementation of star detection and centroid calculation algorithms for star tracking applications

M. B. Ghaznavi-Ghoushchi, Alireza Behrad, Mohsen Azizabadi, 2012, Journal of Real-Time Image Processing.

A 2-bit/step SAR ADC structure with one radix-4 DAC

M. B. Ghaznavi-Ghoushchi, M. H. M. Larijani, 2012, IEICE Electron. Express.

A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements

M. B. Ghaznavi-Ghoushchi, M. Rahimi, 2019, Microelectron. J..

A novel transceiver structure including power and audio amplifiers for Internet of Things applications

M. B. Ghaznavi-Ghoushchi, A. R. Ghorbani, 2017, Comput. Electr. Eng..

TSSL: improving SSL/TLS protocol by trust model

M. B. Ghaznavi-Ghoushchi, Maryam Asadzadeh Kaljahi, Ali Payandeh, 2015, Secur. Commun. Networks.

An ultra low-power digitally controlled oscillator using novel Schmitt-trigger based hysteresis delay cells

Mojtaba Lotfizad, M. B. Ghaznavi-Ghoushchi, Nasser Erfani Majd, 2011, IEICE Electron. Express.

Creating a novel semantic video search engine through enrichment textual and temporal features of subtitled YouTube media fragments

M. B. Ghaznavi-Ghoushchi, Babak Farhadi, 2013, ICCKE 2013.

A 68.8ps jitter, 1.685mw band-selective reconfigurable DCO design for overlapped and non-overlapped applications in 180nm

M. B. Ghaznavi-Ghoushchi, M. Souri, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

A low-power dual band all digital PLL with precision dual mode DCO and digital linearization control circuits

M. B. Ghaznavi-Ghoushchi, M. Souri, A. Abadian, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

Low-complexity and differential power analysis (DPA)-resistant two-folded power-aware Rivest-Shamir-Adleman (RSA) security schema implementation for IoT-connected devices

M. B. Ghaznavi-Ghoushchi, Mohammad-Ali Doostari, Saman Kaedi, 2018, IET Comput. Digit. Tech..

A 14.8 ps jitter low-power dual band all digital PLL with reconfigurable DCO and time-interlined multiplexers

M. B. Ghaznavi-Ghoushchi, M. Souri, 2015 .

A power-performance tunable logic with adjustable threshold pseudo-dynamic building blocks and CMOS compatibility

Naser MohammadZadeh, M. B. Ghaznavi-Ghoushchi, Hanieh Ghaffarishad, 2018, Int. J. Circuit Theory Appl..

A high-precision time-domain RRAM state control approach

M. B. Ghaznavi-Ghoushchi, A. A. Bagheri-Soulla, M. Ghaznavi-Ghoushchi, 2018, Microelectron. J..

A new low power-delay-product, low-area, parallel prefix adder with reduction of graph energy

M. B. Ghaznavi-Ghoushchi, M. Moghaddam, 2011, 2011 19th Iranian Conference on Electrical Engineering.

A low-power low-area architecture design for distributed arithmetic (DA) unit

M. B. Ghaznavi-Ghoushchi, S. F. Ghamkhari, 2012, 20th Iranian Conference on Electrical Engineering (ICEE2012).

MTCML: Analysis, design and optimization of an alternative shallow-depth multiple-tail current mode logic

M. B. Ghaznavi-Ghoushchi, S. A. H. Ejtahed, 2017, Microelectron. J..

A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency

M. B. Ghaznavi-Ghoushchi, M. Rahimi, 2021, Microelectron. J..

A New Low Power Schema for Stream Processors Front-End with Power-Aware DA-Based FIR Filters by Investigation of Image Transitions Sparsity

M. B. Ghaznavi-Ghoushchi, Seyedeh Fatemeh Ghamkhari, 2021, Circuits Syst. Signal Process..

Low-voltage and high-speed stand-alone multiple-input complex gates for error correction coding applications

M. B. Ghaznavi-Ghoushchi, Maliheh Rafiee, 2021, Int. J. Circuit Theory Appl..

Design and Implementation of a CMOS Posicast Pre-Shaper For Vibration Reduction of Op-Amps

M. B. Ghaznavi-Ghoushchi, M. Rasoulzadeh, 2009 .