T. Lii

A High Performance 0.25/spl mu/m CMOS

J. Warnock, K. Jenkins, D. Klaus, 1993, Symposium 1993 on VLSI Technology.

A Room Temperature 0.1 /spl mu/m CMOS on SOI

J. Warnock, S. Furkay, D. Moy, 1993, Symposium 1993 on VLSI Technology.

A highly versatile 0.18 /spl mu/m CMOS technology with dense embedded SRAM

J. Scott, H. Tian, C. Lage, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization

J. Farkas, C. Lage, J. Schmidt, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

The Design, Fabrication and Characterization of 0.15 μm MOS Devices

T. Lii, H. Hanafi, P. Coane, 1993, ESSDERC '93: 23rd European solid State Device Research Conference.