Amitava Chatterjee

发表

A standby current limited performance figure of merit for deep sub-micron CMOS

Richard A. Chapman, T. C. Holloway, V. M. McNeil, 1997 .

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

Amitava Chatterjee, T. Polgreen, 1990 .

New Subject Category on Emerging Technologies and Devices

John D. Cressler, Amitava Chatterjee, Renuka P. Jindal, 2013 .

New Subject Heading on “Memory Devices and Technology”

John D. Cressler, Amitava Chatterjee, 2012 .

An investigation of BiCMOS ESD protection circuit elements and applications in submicron technologies

Amitava Chatterjee, Ajith Amerasekera, 1993 .

Sheet resistance requirements for the source/drain regions of 0.11-μm gate length CMOS technology

Amitava Chatterjee, Ih-Chin Chen, Manoj Mehrotra, 1997, Advanced Lithography.

Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow

Amitava Chatterjee, Thomas L. Polgreen, 1992 .

New Subject Category on Emerging Technologies and Devices

John D. Cressler, Amitava Chatterjee, Renuka P. Jindal, 2013 .

Artificial Neural Network and the Financial Markets: A Survey

Amitava Chatterjee, O. Felix Ayadi, Bryan E. Boone, 2000 .

Intelligent phase correction in automatic digital ac bridges by resilient backpropagation neural network

Amitava Chatterjee, M. Dutta, Anjan Rakshit, 2006 .

Miracle Workers—A Round of Much Deserved Applause for the T-ED and EDL Staff

John D. Cressler, Amitava Chatterjee, 2012 .

Design and simulation of a 4 kV ESD protection circuit for a 0.8 mu m BiCMOS process

Amitava Chatterjee, T. Polgreen, Ajith Amerasekera, 1991, International Electron Devices Meeting 1991 [Technical Digest].

Improved figure-of-merit metric for CMOS transistor performance and its application to 0.25 um CMOS technologies

Amitava Chatterjee, Mark Rodder, Ih-Chin Chen, 1995, Advanced Lithography.

Optimum distributed generation placement with voltage sag effect minimization

Amitava Chatterjee, Swapan Kumar Goswami, Soma Biswas, 2012 .

Pass transistor and isolation design methodology and its implementation for improved manufacturability for 256-Mbit DRAM and beyond

Amitava Chatterjee, Ih-Chin Chen, Mark S. Rodder, 1996, Advanced Lithography.

Palm Dorsa Vein Pattern based biometric verification system using Anisotropic Generalized Procrustes Analysis on weighted training dictionary

Amitava Chatterjee, Sandip Joardar, A. Chatterjee, 2019, Appl. Soft Comput..

New methodology of simulating pocket-implanted sub-0.18-μm CMOS

Amitava Chatterjee, Ih-Chin Chen, J. C. Hu, 1998, Advanced Lithography.

Remote plasma nitrided oxides for ultrathin gate dielectric applications

Amitava Chatterjee, Wei-Tsun Shiau, Jerry C. Hu, 1998, Advanced Lithography.

A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-/spl mu/m CMOS logic technologies

Amitava Chatterjee, Ih-Chin Chen, Mark S. Rodder, 1998 .

Simple Analytical Model of the Thermal Resistance of Resistors in Integrated Circuits

Amitava Chatterjee, Weidong Tian, Doug Weiser, 2010, IEEE Transactions on Electron Devices.

Additional Page for Proper Referencing

Amitava Chatterjee, 2015 .

Short channel transistor and its making method

Amitava Chatterjee, チャッタージーアミタバ, S Rodder Mark, 1996 .

Precision universal temperature ( −200°C to +200°C) controller with fast solid state on-off system

Amitava Chatterjee, S. C. Mukherjee, 1993 .

Study of integration issues in shallow trench isolation for deep submicron CMOS technologies

Amitava Chatterjee, Ih-Chin Chen, John Kuehne, 1996, Advanced Lithography.

Foreword special issue on device integration technology for mixed-signal SOC

A. Matsuzawa, John D. Cressler, D.B.M. Klaassen, 2003 .

Hot-electron reliability and ESD latent damage

Amitava Chatterjee, S. Aur, Thomas L. Polgreen, 1988 .

Dopant Fluctuations and Quantum Effects in Sub-0.1um CMOS

Amitava Chatterjee, Gerhard Klimeck, Ih-Chin Chen, 1997 .

Self-heating effects in basic semiconductor structures

Kartikeya Mayaram, Amitava Chatterjee, Ajith Amerasekera, 1993 .

Hot electron reliability and ESD latent damage

Amitava Chatterjee, S. Aur, Thomas L. Polgreen, 1988 .

Integration of unit processes in a shallow trench isolation module for a 0.25 μm complementary metal–oxide semiconductor technology

Amitava Chatterjee, Ih-Chin Chen, Suhail Murtaza, 1997 .

Correction to "Trench Isolation Step-Induced (TRISI) Narrow Width Effect on MOSFET"

Amitava Chatterjee, Youngmin Kim, Seetharaman Sridhar, 2002 .

A pass transistor design methodology for 256 Mbit DRAM and beyond

Amitava Chatterjee, Ih-Chin Chen, Mark S. Rodder, 1994, Proceedings of 1994 VLSI Technology Symposium.

Parametric study of latchup immunity of deep trench-isolated, bulk, nonepitaxial CMOS

Amitava Chatterjee, J. C. Lee, Al F. Tasch, 1992 .

A Simple Holding Voltage Analysis for Latchup in Epitaxial CMOS

Amitava Chatterjee, Ping Yang, Jerold Seitchik, 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers.

An improved PID-type fuzzy controller employing individual fuzzy P, fuzzy I and fuzzy D controllers

Sugata Munshi, Amitava Chatterjee, A. Chatterjee, 2003 .