Takeshi Kajiyama

FBC (Floating Body Cell) for embedded DRAM on SOI

Hiroaki Yamada, Takashi Ohsawa, Hidemi Ishiuchi, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's

Hiroaki Yamada, Takashi Ohsawa, Takeshi Hamamoto, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

Diagonal layout and surface strap trench (DST) cell [embedded DRAMs]

Mitsuru Sato, Shigeyoshi Watanabe, Takeshi Hamamoto, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Process Integration of Low-Power and High-Speed 16Mb MRAM using Multi-Layer Wiring Technology

S. Miura, Akihiro Nitayama, Hiroaki Yoda, 2006 .

Ion Beam Etching Technology for High-Density Spin Transfer Torque Magnetic Random Access Memory

Akihiro Nitayama, Hiroaki Yoda, Naoharu Shimomura, 2009 .

Effect of novel yoke wire in low-power MRAM applications

Hiroaki Yoda, Shuichi Tahara, Tatsuya Kishi, 2004 .