T. Sansaloni

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

T. Sansaloni, Javier Valls-Coquillat, Asuncion Perez-Pascual, 2009, J. Signal Process. Syst..

Design of an efficient digital down-converter for a SDR-based DVB-S receiver

Javier Valls-Coquillat, Asuncion Perez-Pascual, Vicenç Almenar, 2007, 2007 18th European Conference on Circuit Theory and Design.

A study about FPGA-based digital filters

T. Sansaloni, J. Valls, M.M. Peiro, 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

Fast FPGA-based pipelined digit-serial/parallel multipliers

T. Sansaloni, Javier Valls-Coquillat, Eduardo I. Boemo, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Design and FPGA implementation of digit-serial FIR filters

T. Sansaloni, J. Valls, M.M. Peiro, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA

T. Sansaloni, Javier Valls-Coquillat, Asuncion Perez-Pascual, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes

T. Sansaloni, Javier Valls-Coquillat, Asuncion Perez-Pascual, 2012, J. Signal Process. Syst..

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes

T. Sansaloni, Javier Valls-Coquillat, Ma José Canet, 2012, J. Signal Process. Syst..

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes

J. Valls, A. Pérez-Pascual, T. Sansaloni, 2011, Journal of Signal Processing Systems.

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes

J. Valls, T. Sansaloni, M. J. Canet, 2011, Journal of Signal Processing Systems.

Efficient pipeline FFT processors for WLAN MIMO-OFDM systems

T. Sansaloni, Javier Valls, V. Torres, 2005 .

A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation

M. Martinez-Peiro, J. Valls, T. Sansaloni, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).