Paul-Sen Kan

0 . 339 fJ / bit / search Energy-Efficient TCAM Macro Design in 40 nm LP CMOS

C. Chuang, Po-Tsang Huang, W. Hwang, 2014 .

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.