Kajihara Seiji

发表

Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip

Nishida Toshiya, Wang Senling, Sato Yasuo, 2014 .

Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test

Tanaka Hiroaki, Kajihara Seiji, Miyase Kohei, 2012 .

A Method to Estimate the Number of Don't-Care Bits with Netlist

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2012 .

A Scan-Out Power Reduction Method for Multi-Cycle BIST

Wang Senling, Sato Yasuo, Kajihara Seiji, 2012 .

Locating Hot Spots with Justification Techniques in a Layout Design

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2018 .

An expanded Per-Test X-Fault Diagnosis Method for LSI Circuits

Nakamura Yusuke, Kajihara Seiji, Miyase Kohei, 2007 .

Improving System Dependability by VLSI Test Technology

Kajihara Seiji, 2015 .

An Evaluation of Low Power BIST Method

Wang Senling, Sato Yasuo, Kajihara Seiji, 2012 .

Power Analysis for Logic Area of LSI Including Memory Area

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2020 .

High Field Reliability Using Built-In Self Test

Kajihara Seiji, 2012 .

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test

Kajihara Seiji, Wen Xiaoqing, Yamato Yuta, 2016 .

Design and evaluation of circuits to control scan-in power in logic BIST

Sato Yasuo, Kajihara Seiji, Kato Takaaki, 2013 .

On Avoiding Test Data Corruption by Optimal Scan Chain Grouping

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2017 .

Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2011 .

Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test

Kajihara Seiji, Miura Yukiya, Kato Takaaki, 2019 .

On Machine Learning Based Accuracy Improvement for A Digital Temperature and Voltage Sensor

Kajihara Seiji, Miyake Yousuke, Gondo Masayuki, 2020 .

Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips

Wang Senling, Sato Yasuo, Kajihara Seiji, 2018 .

A Capture-Safe Test Generation Scheme for At-speed Scan Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2008 .

Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification

Kajihara Seiji, Miyase Kohei, Enokimoto Kazunari, 2011 .

Improving Controllability of Signal Transitions in the High Switching Area of LSI

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2020 .

A Temperature Monitor Using Ring-Oscillators on FPGA

Sato Yasuo, Kajihara Seiji, Miyake Yousuke, 2014 .

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2016 .

A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs

Sato Yasuo, Kajihara Seiji, Miyake Yousuke, 2017 .

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2007 .

A method to reduce shift-toggle rate for low power BIST

Wang Senling, Sato Yasuo, Kajihara Seiji, 2012 .

Evaluation of Multi-Cycle Test with Partial Observation in Scan BIST Structure

Sato Yasuo, Kajihara Seiji, Yamaguchi Hisato, 2010 .

Capture power reduction in multi-cycle test structure

Sato Yasuo, Kajihara Seiji, Miyase Kohei, 2011 .

A Constrained Test Generation Method for Low Power Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2007 .

Efficient generation method of indirect implication on ATPG

Kajihara Seiji, Matsunaga Yusuke, Yoshimura Masayoshi, 2006 .

On-chip delay measurement for FPGAs

Abe Kentaro, Sato Yasuo, Kajihara Seiji, 2014 .

Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST

Wang Senling, Sato Yasuo, Kajihara Seiji, 2017 .

Transistor Aging and Operational Environment of Logic Circuits

Sato Yasuo, Kajihara Seiji, Miyase Kohei, 2008 .

IR-Drop Analysis on Different Power Supply Network Designs

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2017 .

Improving Controllability of Switching Activity for Specified Areas in the LSI

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2020 .

A Method to Identify High Test Power Areas in Layout Design

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2015 .

On-Chip Delay Measurement for In-field Periodic Test of FPGAs

Sato Yasuo, Kajihara Seiji, Miyake Yousuke, 2018 .

On Finding Don't Cares in Test Sequences for Sequential Circuits and Applications to Test Compaction and Power Reduction

Kajihara Seiji, Higami Yoshinobu, Kobayashi Shin-ya, 2005 .

A theretical discussion for testabilty of a degraded LSI in field

Sato Yasuo, Kajihara Seiji, 2013 .

On Correction of Temperature Influence to Delay Measurement in FPGAs

Sato Yasuo, Kajihara Seiji, Kina Takeru, 2015 .

Variable Test-Timing Generation for Built-In Self-Test on FPGA

Sato Yasuo, Kajihara Seiji, Matsuura Munehiro, 2013 .