Tiberiu Chelcea

发表

A burst-mode oriented back-end for the Balsa synthesis system

Doug A. Edwards, Steven M. Nowick, Andrew Bardsley, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems

Steven M. Nowick, Tiberiu Chelcea, 2002, DAC '02.

HLS Support for Unconstrained Memory Accesses

Seth Copen Goldstein, Girish Venkataramani, Tiberiu Chelcea, 2005 .

Low-latency asynchronous FIFO's using token rings

Steven M. Nowick, Tiberiu Chelcea, 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

C to Asynchronous Dataflow Circuits: An End-to-End Toolflow

Seth Copen Goldstein, Mihai Budiu, Girish Venkataramani, 2004 .

Hardware compilation of application-specific memory-access interconnect

Seth Copen Goldstein, Girish Venkataramani, Tobias Bjerregaard, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The Design of Low-Latency Interfaces for Mixed-Timing Systems

Steven M. Nowick, Tiberiu Chelcea, 2001 .

Tartan: evaluating spatial computation for whole program execution

Seth Copen Goldstein, Mihai Budiu, Girish Venkataramani, 2006, ASPLOS XII.

Global Critical Path: A Tool for System-Level Timing Analysis

Seth Copen Goldstein, Mihai Budiu, Girish Venkataramani, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Adding Faster with Application Specific Early Termination

David Ryan Koes, Seth Copen Goldstein, Tiberiu Chelcea, 2005 .

Spatial computation

Seth Copen Goldstein, Mihai Budiu, Girish Venkataramani, 2004, ASPLOS XI.

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Seth Copen Goldstein, Girish Venkataramani, Tiberiu Chelcea, 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).

Heterogeneous Latch-Based Asynchronous Pipelines

Seth Copen Goldstein, Girish Venkataramani, Tiberiu Chelcea, 2008, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.

Self-Resetting Latches for Asynchronous Micro-Pipelines

Seth Copen Goldstein, Girish Venkataramani, Tiberiu Chelcea, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Robust interfaces for mixed-timing systems

Steven M. Nowick, Tiberiu Chelcea, S. Nowick, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SOMA: a tool for synthesizing and optimizing memory accesses in ASICs

Seth Copen Goldstein, Girish Venkataramani, Tobias Bjerregaard, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

A low-latency FIFO for mixed-clock systems

Steven M. Nowick, Tiberiu Chelcea, S. Nowick, 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

Steven M. Nowick, Tiberiu Chelcea, S. Nowick, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Design and optimization of large-scale asynchronous and mixed-timing systems

Steven M. Nowick, Tiberiu Chelcea, 2004 .

The Design of Low-Latency Interfaces The Design of Low-Latency Interfaces for Mixed-Timing Systems for Mixed-Timing Systems

Steven M. Nowick, Tiberiu Chelcea, 2002 .

Modeling the Global Critical Path in Concurrent Systems

Seth Copen Goldstein, Mihai Budiu, Girish Venkataramani, 2006 .

Balsa-CUBE: an Optimizing Back-End for the Balsa Synthesis System

Steven M. Nowick, Andrew Bardsley, Doug Edwards, .