Tay-Jyi Lin

发表

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

Chih-Wei Liu, Tay-Jyi Lin, Yu-Ting Kuo, 2008, J. Signal Process. Syst..

Data stream generation for concurrent computation in VLSI signal processors

Chein-Wei Jen, Tay-Jyi Lin, C. Jen, 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

Data Stream Generation for Concurrent Computation in

Vlsi Signal Processors, Tay-Jyi Lin, Tay-Jyi Lin, 2000 .

A unified processor architecture for RISC & VLIW DSP

Chein-Wei Jen, Chih-Wei Liu, Tay-Jyi Lin, 2005, ACM Great Lakes Symposium on VLSI.

An efficient VLIW DSP architecture for baseband processing

Chein-Wei Jen, Tay-Jyi Lin, Chen-Chia Lee, 2003, Proceedings 21st International Conference on Computer Design.

On-demand Pipelining for Improving Energy-Awareness

Chein-Wei Jen, Tay-Jyi Lin, Chin-Hung Liu, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

Coefficient optimization for area-effective multiplier-less FIR filters

Chein-Wei Jen, Tsung-Hsun Yang, Tay-Jyi Lin, 2003, 2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698).

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations

Tien-Fu Chen, Wei-Chung Cheng, Jinn-Shyan Wang, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters

Chih-Wei Liu, Tay-Jyi Lin, Yu-Ting Kuo, 2011, EURASIP J. Adv. Signal Process..

Improving energy efficiency of functional units by exploiting their data-dependent latency

Chih-Wei Liu, Yen-Cheng Lin, Shih-Hao Ou, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Improving datapath utilization of programmable DSP with composite functional units

Chih-Wei Liu, Shih-Hao Ou, Tay-Jyi Lin, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Rapid C to FPGA Prototyping with Multithreaded Emulation Engine

Chih-Wei Liu, Tay-Jyi Lin, Shin-Kai Chen, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Latency-Tolerant Virtual Cluster Architecture for VLIW DSP

Chein-Wei Jen, Chih-Wei Liu, Tay-Jyi Lin, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes

Chih-Wei Liu, Shih-Hao Ou, Tay-Jyi Lin, 2007, 2007 Asia and South Pacific Design Automation Conference.

A Compact DSP Core with Static Floating-Point Arithmetic

Chih-Wei Liu, Chih-Wei Jen, Tay-Jyi Lin, 2006, J. VLSI Signal Process..

A 52mW 1200MIPS compact DSP for multi-core media SoC

Chein-Wei Jen, Chih-Wei Liu, Shih-Hao Ou, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Hierarchical instruction encoding for VLIW digital signal processors

Chein-Wei Jen, Chih-Wei Liu, Tay-Jyi Lin, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A compact DSP core with static floating-point unit & its microcode generation

Chein-Wei Jen, Chih-Wei Liu, Tay-Jyi Lin, 2004, GLSVLSI '04.

Performance evaluation of ring-structure register file in multimedia applications

Chein-Wei Jen, Tsung-Hsun Yang, Chien-Hung Lin, 2003, 2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698).

CASCADE - configurable and scalable DSP environment

Chein-Wei Jen, Tay-Jyi Lin, C. Jen, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).