Soo In Cho

A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology

Jae Young Lee, Kye Hyun Kyung, Chi Wook Kim, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

data transmission circuit in CMOS DRAM

Soo In Cho, Yong Eue Park, Dong Jun Soo, 1988 .

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Changsik Yoo, Soo In Cho, Chang Ho Lee, 1999 .

A Low Power 1 GByte/sec Synchronous Interface

Kye Hyun Kyung, Soo In Cho, Changhyun Kim, 1997 .

A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

Woo Jin Lee, Young Cheol Cho, Dae Hyun Jeong, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 2.5 V 333 Mb/s/pin 1 Gb double data rate SDRAM

Soo In Cho, Hongil Yoon, Tae-Sung Jung, 1999 .

A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme

Kye Hyun Kyung, Chul Soo Kim, Byung Hoon Jeong, 2007, 2007 IEEE Symposium on VLSI Circuits.

1Gbit DDR SDRAM for Low Voltage and High Speed Application (Invited)

Soo In Cho, Hongil Yoon, Tae Young Ko, 1999 .

boost voltage generator of a memory device semiconductor

Soo In Cho, Hyun-Seok Lee, 1996 .

Investigation of Requirements for High-Speed DRAM Interface using Rambus-C as an Example

Soo In Cho, Hong June Park, Jong Sun Kim, 1997 .

HIGH PERFORMANCE LOW Vcc DRAM`S WITH THE IVC USING Vcc DETECTING SCHEME

Jei Hwan Yoo, Soo In Cho, Hyung-Kyu Lim, 1995 .