Hua-Yu Chang

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification

Yao-Wen Chang, Iris Hui-Ru Jiang, Hua-Yu Chang, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ECOS: Stable Matching Based Metal-Only ECO Synthesis

Iris Hui-Ru Jiang, Hua-Yu Chang, I. Jiang, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations

Sani R. Nassif, Gi-Joon Nam, Iris Hui-Ru Jiang, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Timing ECO optimization using metal-configurable gate-array spare cells

Yao-Wen Chang, Iris Hui-Ru Jiang, Hua-Yu Chang, 2012, DAC Design Automation Conference 2012.

WiT: Optimal Wiring Topology for Electromigration Avoidance

Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Matching-based minimum-cost spare cell selection for design changes

Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles

Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang, 2010, ISPD '10.