J. Anwer

Computation and analysis of output error probability for C17 benchmark circuit using bayesian networks error modeling

Narinderjit Singh, Vijanth S. Asirvadam, Jahanzeb Anwer, 2010, 2010 IEEE Student Conference on Research and Development (SCOReD).

FPGA Redundancy Configurations: An Automated Design Space Exploration

Marco Platzner, Jahanzeb Anwer, Sebastian Meisner, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

Reliability-evaluation of digital circuits using probabilistic computation schemes

Narinderjit Singh, Vijanth S. Asirvadam, Jahanzeb Anwer, 2011, 2011 National Postgraduate Conference.

The Impact of Sensitive Inputs on the Reliability of Nanoscale Circuits

Nor Hisham Hamid, Vijanth S. Asirvadam, Jahanzeb Anwer, 2015, Computational Intelligence in Digital and Network Designs and Applications.

Determination of worst case input combinations of nanoscale circuits using Bayesian networks

V. S. Asirvadam, N. H. Hamid, U. Khalid, 2012, 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012).