A. Jain

Methodology to Estimate Robustness of Layouts of Radiation Hardened Flip-Flops to High Energy Radiations

Anuj Grover, Kamakshi Pandey, A. Jain, 2020, IEEE India Conference.

A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder

Gilles Sicard, Sylvain Clerc, Fady Abouzeid, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL pdf

Krishna Kumar, Abhishek Jain, Hima Gupta, 2014, ArXiv.

Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs pdf

Ajay Goyal, Abhishek Jain, Hima Gupta, 2012, VLSIC 2012.

ACCELERATING SYSTEM VERILOG UVM BASED VIP pdf

Abhishek Jain, Piyush Kumar Gupta, Hima Gupta, 2014 .

The Evolution of Domain-Specific Computing for Deep Learning

S. Neuendorffer, K. Denolf, Alireza Khodamoradi, 2021, IEEE Circuits and Systems Magazine.

Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform

Dinesh Gaitonde, Abhishek Kumar Jain, Sharan Kumar, 2021, 2021 IEEE High Performance Extreme Computing Conference (HPEC).

Architecture centric coarse-grained FPGA overlays

Abhishek Kumar Jain, A. Jain, 2017 .

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain, 2016, 2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech).

An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units pdf

Douglas L. Maskell, Suhaib A. Fahmy, Xiangwei Li, 2016, ArXiv.

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect

Douglas L. Maskell, Suhaib A. Fahmy, Xiangwei Li, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq

Douglas L. Maskell, Suhaib A. Fahmy, Xiangwei Li, 2016, SIGARCH Comput. Archit. News.

Throughput oriented FPGA overlays using DSP blocks

Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Efficient Overlay Architecture Based on DSP Blocks

Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform

Suhaib A. Fahmy, D. Maskell, Jin Cui, 2014, J. Signal Process. Syst..

Microkernel hypervisor for a hybrid ARM-FPGA platform

Douglas L. Maskell, Suhaib A. Fahmy, Khoa Dang Pham, 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay

Douglas L. Maskell, Suhaib A. Fahmy, Xiangwei Li, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).