Pooja Batra

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

Kaushik Roy, Swaroop Ghosh, Pooja Batra, 2007, 2007 IEEE Custom Integrated Circuits Conference.

An Efficient Approach for Test Suite Reduction using Density based Clustering Technique

Pooja Batra, Rashi Chauhan, Sarika Chaudhary, 2014 .

Comparative Study of Link Analysis Algorithms

Asha Sohal, Pooja Batra, Aditya Upadhyay, 2013 .

Criticality Estimation for Software Components: An Empirical Approach

Maitreyee Dutta, Arun Sharma, Pooja Batra, 2012 .

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

Toshiaki Kirihata, John Golz, Alex Hubbard, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).