H.G. Kerkhoff

Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations

H.J. VerMaak, H.G. Kerkhoff, 2001, IEEE European Test Workshop, 2001..

VHDL-AMS fault simulation for testing DNA bio-sensing arrays

H.G. Kerkhoff, F. Azais, P. Nouet, 2005, IEEE Sensors, 2005..

Jitter and decision-level noise separation in A/D converters

R.J.W.T. Tangelder, H.G. Kerkhoff, M. Sachdev, 1999, IMTC/99. Proceedings of the 16th IEEE Instrumentation and Measurement Technology Conference (Cat. No.99CH36309).

Control electronics for a neuro-electronic interface implemented in a gate array

H.G. Kerkhoff, W.L.C. Rutten, T.A. Frieswijk, 1995, Proceedings of 17th International Conference of the Engineering in Medicine and Biology Society.

An implementation for test-time reduction in VLIW transport-triggered architectures

H.G. Kerkhoff, V.A. Zivkovic, R.J.W. Tangelder, 2001, IEEE European Test Workshop, 2001..

Scan cell design for enhanced delay fault testability

H.G. Kerkhoff, Y. Xing, G. van Brakel, 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

Design and implementation of a hierarchical testable architecture using the boundary scan standard

H.G. Kerkhoff, R.P. van Riessen, A. Kloppenburg, 1989, [1989] Proceedings of the 1st European Test Conference.